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  </head><body>
            
            <div class="regmap">
              <a name="ZBX_CPLD"></a>
              <h1 class="regmap">ZBX_CPLD</h1>
            
            <p>The top is defined in HDL source file zbx_top_cpld.v.</p>
            <div class="group"><a name="P1 Content"></a><h2 class="group">P1 Content</h2>
            <div class="register"><h3 class="register">Register map for 'ZBX_CPLD' core team members</h3>
            <i>This content is intended solely for use by core team members of the 'ZBX_CPLD' project.
                   Do not distribute or otherwise forward this content.  If you believe you have acquired
                   access to this content in error, delete it immediately and notify the sender that you
                   are not intended to have access to this content.<BR/><BR/>"All content provided is NI Confidential and Copyright 2022 National Instruments Corporation.
For information on NI trademark guidelines, please see <a href="http://www.ni.com/legal/trademarks/">http://www.ni.com/legal/trademarks/</a>. For the NI Patent Notice, please see <a href="http://www.ni.com/legal/patents/">http://www.ni.com/legal/patents/</a>."
            </i></div><BR/>
</div>

            <div class="group"><a name="ports"></a><h2 class="group">ports</h2>
            This section lists all common communication interfaces of the ZBX CPLD.
      Each input port will point to a regmap. The SPI port can reach out to
      each register. The GPIO port can access a subset of all register, where
      the use case is mainly RF configuration to enable fast changes.
            <div class="register">
              <a name="ZBX_CPLD|GPIO"></a>
            
<h3 class="register">Port GPIO (input)</h3>

             <p class="offset_info">
             
                    Target Regmap = <a href="#GPIO_REGMAP">GPIO_REGMAP</a>
                
</p>

<div class="info">

Controlport requests from the FPGA GPIO lines.

</div>

                <p class="reg_info">
                    This port is defined in HDL source file zbx_top_cpld.v.
                </p>
                
</div>

            <div class="register">
              <a name="ZBX_CPLD|SPI"></a>
            
<h3 class="register">Port SPI (input)</h3>

             <p class="offset_info">
             
                    Target Regmap = <a href="#SPI_REGMAP">SPI_REGMAP</a>
                
</p>

<div class="info">

Controlport requests from this SPI interface are driven by the PL part
        of the RFSoC via the MB CPLD.

</div>

                <p class="reg_info">
                    This port is defined in HDL source file zbx_top_cpld.v.
                </p>
                
</div>

</div>

</div>

            <div class="regmap">
              <a name="ATR_REGMAP"></a>
              <h1 class="regmap">ATR_REGMAP</h1>
            
            <div class="group"><a name="ATR_REGMAP|ATR_REGISTERS"></a><h2 class="group">ATR_REGISTERS</h2>
            This regmap contains settings for the active configuration of RF 0 and 1.
     There are two sets of configurations. One set comprises RF switches and
     LEDs, the other set comprises the attenuators (DSA).
            <div class="enum">
              <a name="ATR_REGMAP|ATR_OPTIONS"></a>
            
<h3 class="enum">ATR_OPTIONS Enumeration</h3>
Contains the options available for RF 0 and RF 1. The chosen setting
        affects how the active configuration of up to 8 bits is derived.
            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' > Value </td>
                    <td class="l"   colspan='1'> Name </td>
                    
</tr>

<tr valign="top">

                        <td class='value'>0</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|SW_DEFINED'></a>SW_DEFINED</p>
                            
<p class="l">Uses the respective value of <a href="#ATR_REGMAP|SW_CONFIG_REG">SW_CONFIG_REG</a> as configuration.

</td>

</tr>

<tr valign="top">

                        <td class='value'>1</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|CLASSIC_ATR'></a>CLASSIC_ATR</p>
                            
<p class="l">This option assumes the FPGA state to be assigned with: Bit 0 = RF 0
          RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3
          = RF 1 TX running. The configuration for each RF chain is built
          up of the 2 bits for the RF chain (4 possible states: IDLE, RX only,
          TX only, TX/RX).

</td>

</tr>

<tr valign="top">

                        <td class='value'>2</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|FPGA_STATE'></a>FPGA_STATE</p>
                            
<p class="l">The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.

</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file atr_controller.v.
                </p>
                
</div>

            <div class="register">
              <a name="ATR_REGMAP|CURRENT_CONFIG_REG"></a>
            
<h3 class="register">Offset 0x0000: CURRENT_CONFIG_REG Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('ATR_REGMAP|CURRENT_CONFIG_REG_in')">(<span id="show_ATR_REGMAP|CURRENT_CONFIG_REG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_ATR_REGMAP|CURRENT_CONFIG_REG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS">DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">CURRENT_CONFIG_REG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001000

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001000

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file atr_controller.v.</p>

</div>

<div class="info">

Contains the current active configuration.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|CURRENT_CONFIG_REG|CURRENT_RF1_DSA_CONFIG"></a>CURRENT_RF1_DSA_CONFIG</span><span class="attr"> </span></p>
                <p>Current active configuration for DSAs of RF 1.</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|CURRENT_CONFIG_REG|CURRENT_RF0_DSA_CONFIG"></a>CURRENT_RF0_DSA_CONFIG</span><span class="attr"> </span></p>
                <p>Current active configuration for DSAs of RF 0.</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..8</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|CURRENT_CONFIG_REG|CURRENT_RF1_CONFIG"></a>CURRENT_RF1_CONFIG</span><span class="attr"> </span></p>
                <p>Current active configuration for switches and LEDs of RF 1.</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..0</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|CURRENT_CONFIG_REG|CURRENT_RF0_CONFIG"></a>CURRENT_RF0_CONFIG</span><span class="attr"> </span></p>
                <p>Current active configuration for switches and LEDs of RF 0.</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="ATR_REGMAP|OPTION_REG"></a>
            
<h3 class="register">Offset 0x0004: OPTION_REG Register (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('ATR_REGMAP|OPTION_REG_in')">(<span id="show_ATR_REGMAP|OPTION_REG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_ATR_REGMAP|OPTION_REG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS">DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">OPTION_REG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0004</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001004

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001004

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value = 0x00000000
</p>

<p class="reg_info">This register is defined in HDL source file atr_controller.v.</p>

</div>

<div class="info">

Set the option to be used for the RF chains.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..26</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">25..24</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|OPTION_REG|RF1_DSA_OPTION"></a>RF1_DSA_OPTION</span><span class="attr"> &nbsp;&nbsp;(initialvalue=SW_DEFINED)</span></p>
                <p>Option used for DSAs of RF 1.</p>
            
                    <p>
                      The values for this bitfield are in the <a href="#ATR_REGMAP|ATR_OPTIONS">ATR_OPTIONS</a> table.
                      <a class="sh_enum" href="javascript:sb('ATR_REGMAP|OPTION_REG|RF1_DSA_OPTION')">(<span id="show_ATR_REGMAP|OPTION_REG|RF1_DSA_OPTION">show here</span>)</a>
                    </p>
                    <div class="sh_enum" id="div_ATR_REGMAP|OPTION_REG|RF1_DSA_OPTION">
                    
            <div class="enum">
              <a name="ATR_REGMAP|ATR_OPTIONS"></a>
            Contains the options available for RF 0 and RF 1. The chosen setting
        affects how the active configuration of up to 8 bits is derived.
            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' > Value </td>
                    <td class="l"   colspan='1'> Name </td>
                    
</tr>

<tr valign="top">

                        <td class='value'>0</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|SW_DEFINED'></a>SW_DEFINED</p>
                            
<p class="l">Uses the respective value of <a href="#ATR_REGMAP|SW_CONFIG_REG">SW_CONFIG_REG</a> as configuration.

</td>

</tr>

<tr valign="top">

                        <td class='value'>1</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|CLASSIC_ATR'></a>CLASSIC_ATR</p>
                            
<p class="l">This option assumes the FPGA state to be assigned with: Bit 0 = RF 0
          RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3
          = RF 1 TX running. The configuration for each RF chain is built
          up of the 2 bits for the RF chain (4 possible states: IDLE, RX only,
          TX only, TX/RX).

</td>

</tr>

<tr valign="top">

                        <td class='value'>2</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|FPGA_STATE'></a>FPGA_STATE</p>
                            
<p class="l">The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.

</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file atr_controller.v.
                </p>
                
</div>

</div>

              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..18</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">17..16</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|OPTION_REG|RF0_DSA_OPTION"></a>RF0_DSA_OPTION</span><span class="attr"> &nbsp;&nbsp;(initialvalue=SW_DEFINED)</span></p>
                <p>Option used for DSAs of RF 0.</p>
            
                    <p>
                      The values for this bitfield are in the <a href="#ATR_REGMAP|ATR_OPTIONS">ATR_OPTIONS</a> table.
                      <a class="sh_enum" href="javascript:sb('ATR_REGMAP|OPTION_REG|RF0_DSA_OPTION')">(<span id="show_ATR_REGMAP|OPTION_REG|RF0_DSA_OPTION">show here</span>)</a>
                    </p>
                    <div class="sh_enum" id="div_ATR_REGMAP|OPTION_REG|RF0_DSA_OPTION">
                    
            <div class="enum">
              <a name="ATR_REGMAP|ATR_OPTIONS"></a>
            Contains the options available for RF 0 and RF 1. The chosen setting
        affects how the active configuration of up to 8 bits is derived.
            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' > Value </td>
                    <td class="l"   colspan='1'> Name </td>
                    
</tr>

<tr valign="top">

                        <td class='value'>0</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|SW_DEFINED'></a>SW_DEFINED</p>
                            
<p class="l">Uses the respective value of <a href="#ATR_REGMAP|SW_CONFIG_REG">SW_CONFIG_REG</a> as configuration.

</td>

</tr>

<tr valign="top">

                        <td class='value'>1</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|CLASSIC_ATR'></a>CLASSIC_ATR</p>
                            
<p class="l">This option assumes the FPGA state to be assigned with: Bit 0 = RF 0
          RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3
          = RF 1 TX running. The configuration for each RF chain is built
          up of the 2 bits for the RF chain (4 possible states: IDLE, RX only,
          TX only, TX/RX).

</td>

</tr>

<tr valign="top">

                        <td class='value'>2</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|FPGA_STATE'></a>FPGA_STATE</p>
                            
<p class="l">The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.

</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file atr_controller.v.
                </p>
                
</div>

</div>

              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..10</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">9..8</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|OPTION_REG|RF1_OPTION"></a>RF1_OPTION</span><span class="attr"> &nbsp;&nbsp;(initialvalue=SW_DEFINED)</span></p>
                <p>Option used for switches and LEDs of RF 1.</p>
            
                    <p>
                      The values for this bitfield are in the <a href="#ATR_REGMAP|ATR_OPTIONS">ATR_OPTIONS</a> table.
                      <a class="sh_enum" href="javascript:sb('ATR_REGMAP|OPTION_REG|RF1_OPTION')">(<span id="show_ATR_REGMAP|OPTION_REG|RF1_OPTION">show here</span>)</a>
                    </p>
                    <div class="sh_enum" id="div_ATR_REGMAP|OPTION_REG|RF1_OPTION">
                    
            <div class="enum">
              <a name="ATR_REGMAP|ATR_OPTIONS"></a>
            Contains the options available for RF 0 and RF 1. The chosen setting
        affects how the active configuration of up to 8 bits is derived.
            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' > Value </td>
                    <td class="l"   colspan='1'> Name </td>
                    
</tr>

<tr valign="top">

                        <td class='value'>0</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|SW_DEFINED'></a>SW_DEFINED</p>
                            
<p class="l">Uses the respective value of <a href="#ATR_REGMAP|SW_CONFIG_REG">SW_CONFIG_REG</a> as configuration.

</td>

</tr>

<tr valign="top">

                        <td class='value'>1</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|CLASSIC_ATR'></a>CLASSIC_ATR</p>
                            
<p class="l">This option assumes the FPGA state to be assigned with: Bit 0 = RF 0
          RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3
          = RF 1 TX running. The configuration for each RF chain is built
          up of the 2 bits for the RF chain (4 possible states: IDLE, RX only,
          TX only, TX/RX).

</td>

</tr>

<tr valign="top">

                        <td class='value'>2</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|FPGA_STATE'></a>FPGA_STATE</p>
                            
<p class="l">The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.

</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file atr_controller.v.
                </p>
                
</div>

</div>

              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..2</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">1..0</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|OPTION_REG|RF0_OPTION"></a>RF0_OPTION</span><span class="attr"> &nbsp;&nbsp;(initialvalue=SW_DEFINED)</span></p>
                <p>Option used for switches and LEDs of RF 0.</p>
            
                    <p>
                      The values for this bitfield are in the <a href="#ATR_REGMAP|ATR_OPTIONS">ATR_OPTIONS</a> table.
                      <a class="sh_enum" href="javascript:sb('ATR_REGMAP|OPTION_REG|RF0_OPTION')">(<span id="show_ATR_REGMAP|OPTION_REG|RF0_OPTION">show here</span>)</a>
                    </p>
                    <div class="sh_enum" id="div_ATR_REGMAP|OPTION_REG|RF0_OPTION">
                    
            <div class="enum">
              <a name="ATR_REGMAP|ATR_OPTIONS"></a>
            Contains the options available for RF 0 and RF 1. The chosen setting
        affects how the active configuration of up to 8 bits is derived.
            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' > Value </td>
                    <td class="l"   colspan='1'> Name </td>
                    
</tr>

<tr valign="top">

                        <td class='value'>0</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|SW_DEFINED'></a>SW_DEFINED</p>
                            
<p class="l">Uses the respective value of <a href="#ATR_REGMAP|SW_CONFIG_REG">SW_CONFIG_REG</a> as configuration.

</td>

</tr>

<tr valign="top">

                        <td class='value'>1</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|CLASSIC_ATR'></a>CLASSIC_ATR</p>
                            
<p class="l">This option assumes the FPGA state to be assigned with: Bit 0 = RF 0
          RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3
          = RF 1 TX running. The configuration for each RF chain is built
          up of the 2 bits for the RF chain (4 possible states: IDLE, RX only,
          TX only, TX/RX).

</td>

</tr>

<tr valign="top">

                        <td class='value'>2</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='ATR_REGMAP|ATR_OPTIONS|FPGA_STATE'></a>FPGA_STATE</p>
                            
<p class="l">The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.

</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file atr_controller.v.
                </p>
                
</div>

</div>

              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="ATR_REGMAP|SW_CONFIG_REG"></a>
            
<h3 class="register">Offset 0x0008: SW_CONFIG_REG Register (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('ATR_REGMAP|SW_CONFIG_REG_in')">(<span id="show_ATR_REGMAP|SW_CONFIG_REG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_ATR_REGMAP|SW_CONFIG_REG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS">DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">SW_CONFIG_REG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0008</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001008

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001008

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value = 0x00000000
</p>

<p class="reg_info">This register is defined in HDL source file atr_controller.v.</p>

</div>

<div class="info">

Contains the configuration to be applied in case SW_DEFINED option is
       chosen.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|SW_CONFIG_REG|SW_RF1_DSA_CONFIG"></a>SW_RF1_DSA_CONFIG</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>SW defined configuration for DSAs of RF 1.</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|SW_CONFIG_REG|SW_RF0_DSA_CONFIG"></a>SW_RF0_DSA_CONFIG</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>SW defined configuration for DSAs of RF 0.</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..8</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|SW_CONFIG_REG|SW_RF1_CONFIG"></a>SW_RF1_CONFIG</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>SW defined configuration for switches and LEDs of RF 1.</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..0</td>
              <td>
                <p><span class="name"><a name="ATR_REGMAP|SW_CONFIG_REG|SW_RF0_CONFIG"></a>SW_RF0_CONFIG</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>SW defined configuration for switches and LEDs of RF 0.</p>
            
              </td>
            </tr>
            
</table>

</div>

</div>

</div>

            <div class="regmap">
              <a name="BASIC_REGS_REGMAP"></a>
              <h1 class="regmap">BASIC_REGS_REGMAP</h1>
            
            <div class="group"><a name="BASIC_REGS_REGMAP|BASIC_REGS_REGISTERS"></a><h2 class="group">BASIC_REGS_REGISTERS</h2>
            This regmap contains the revision registers, signature register, a scratch register, and a slave control reg.
            <div class="enum">
              <a name="BASIC_REGS_REGMAP|BASIC_REGISTERS_VALUES"></a>
            
<h3 class="enum">BASIC_REGISTERS_VALUES Enumeration</h3>
This enum is used to create the constants held in the basic registers in both verilog and vhdl.
            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' colspan='2'> Value </td>
                    <td class="l"  rowspan='2' colspan='1'> Name </td>
                    
</tr>

<tr class="header2" valign="bottom">

<td class='value'> Dec </td>

<td class='l'> Hex </td>

</tr>

<tr valign="top">

                        <td class='value'>16386</td>
                        
                            <td class='l'>0x00004002</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='BASIC_REGS_REGMAP|BASIC_REGISTERS_VALUES|BOARD_ID_VALUE'></a>BOARD_ID_VALUE</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>5063000</td>
                        
                            <td class='l'>0x004D4158</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='BASIC_REGS_REGMAP|BASIC_REGISTERS_VALUES|VARIANT_ID_MAX10'></a>VARIANT_ID_MAX10</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>5787443</td>
                        
                            <td class='l'>0x00584F33</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='BASIC_REGS_REGMAP|BASIC_REGISTERS_VALUES|VARIANT_ID_XO3'></a>VARIANT_ID_XO3</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>537986577</td>
                        
                            <td class='l'>0x20110611</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='BASIC_REGS_REGMAP|BASIC_REGISTERS_VALUES|OLDEST_CPLD_REVISION'></a>OLDEST_CPLD_REVISION</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>570958387</td>
                        
                            <td class='l'>0x22082233</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='BASIC_REGS_REGMAP|BASIC_REGISTERS_VALUES|CPLD_REVISION'></a>CPLD_REVISION</p>
                            
</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file basic_regs.v.
                </p>
                
</div>

            <div class="register">
              <a name="BASIC_REGS_REGMAP|SLAVE_SIGNATURE"></a>
            
<h3 class="register">Offset 0x0000: SLAVE_SIGNATURE Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('BASIC_REGS_REGMAP|SLAVE_SIGNATURE_in')">(<span id="show_BASIC_REGS_REGMAP|SLAVE_SIGNATURE_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_BASIC_REGS_REGMAP|SLAVE_SIGNATURE_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|BASE_WINDOW_GPIO">GPIO_REGMAP|BASE_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">SLAVE_SIGNATURE</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000000

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|BASE_WINDOW_SPI">SPI_REGMAP|BASE_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000000

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file basic_regs.v.</p>

</div>

<div class="info">

This register contains the unique signature of the DB. This signature is the same value as the one
       stored on the board ID EEPROM

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..0</td>
              <td>
                <p><span class="name"><a name="BASIC_REGS_REGMAP|SLAVE_SIGNATURE|BOARD_ID"></a>BOARD_ID</span><span class="attr"> </span></p>
                <p>Board ID corresponds to the las 16 digits of the daughterboard part number.</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="BASIC_REGS_REGMAP|SLAVE_REVISION"></a>
            
<h3 class="register">Offset 0x0004: SLAVE_REVISION Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('BASIC_REGS_REGMAP|SLAVE_REVISION_in')">(<span id="show_BASIC_REGS_REGMAP|SLAVE_REVISION_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_BASIC_REGS_REGMAP|SLAVE_REVISION_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|BASE_WINDOW_GPIO">GPIO_REGMAP|BASE_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">SLAVE_REVISION</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0004</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000004

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|BASE_WINDOW_SPI">SPI_REGMAP|BASE_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000004

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file basic_regs.v.</p>

</div>

<div class="info">

This register contains the revision number of the current build

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..0</td>
              <td>
                <p><span class="name"><a name="BASIC_REGS_REGMAP|SLAVE_REVISION|REVISION_REG"></a>REVISION_REG</span><span class="attr"> </span></p>
                <p>Returns the revision in YYMMDDHH format</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="BASIC_REGS_REGMAP|SLAVE_OLDEST_REVISION"></a>
            
<h3 class="register">Offset 0x0008: SLAVE_OLDEST_REVISION Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('BASIC_REGS_REGMAP|SLAVE_OLDEST_REVISION_in')">(<span id="show_BASIC_REGS_REGMAP|SLAVE_OLDEST_REVISION_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_BASIC_REGS_REGMAP|SLAVE_OLDEST_REVISION_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|BASE_WINDOW_GPIO">GPIO_REGMAP|BASE_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">SLAVE_OLDEST_REVISION</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0008</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000008

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|BASE_WINDOW_SPI">SPI_REGMAP|BASE_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000008

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file basic_regs.v.</p>

</div>

<div class="info">

This register contains the revision number of the oldest compatible revision

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..0</td>
              <td>
                <p><span class="name"><a name="BASIC_REGS_REGMAP|SLAVE_OLDEST_REVISION|OLDEST_REVISION_REG"></a>OLDEST_REVISION_REG</span><span class="attr"> </span></p>
                <p>Returns the oldest compatible revision in YYMMDDHH format</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="BASIC_REGS_REGMAP|SLAVE_SCRATCH"></a>
            
<h3 class="register">Offset 0x000C: SLAVE_SCRATCH Register (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('BASIC_REGS_REGMAP|SLAVE_SCRATCH_in')">(<span id="show_BASIC_REGS_REGMAP|SLAVE_SCRATCH_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_BASIC_REGS_REGMAP|SLAVE_SCRATCH_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|BASE_WINDOW_GPIO">GPIO_REGMAP|BASE_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">SLAVE_SCRATCH</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x000C</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00000C

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|BASE_WINDOW_SPI">SPI_REGMAP|BASE_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00000C

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value = 0x00000000
</p>

<p class="reg_info">This register is defined in HDL source file basic_regs.v.</p>

</div>

<div class="info">

Read/write scratch register

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..0</td>
              <td>
                <p><span class="name"><a name="BASIC_REGS_REGMAP|SLAVE_SCRATCH|SCRATCH_REG"></a>SCRATCH_REG</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Returns the value written here previously.</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="BASIC_REGS_REGMAP|GIT_HASH_REGISTER"></a>
            
<h3 class="register">Offset 0x0010: GIT_HASH_REGISTER Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('BASIC_REGS_REGMAP|GIT_HASH_REGISTER_in')">(<span id="show_BASIC_REGS_REGMAP|GIT_HASH_REGISTER_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_BASIC_REGS_REGMAP|GIT_HASH_REGISTER_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|BASE_WINDOW_GPIO">GPIO_REGMAP|BASE_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">GIT_HASH_REGISTER</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0010</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000010

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|BASE_WINDOW_SPI">SPI_REGMAP|BASE_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000010

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file basic_regs.v.</p>

</div>

<div class="info">

Git hash of commit used to build this image.<br>
        Value equals 0xDEADBEEF if the git hash was not used during synthesis.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..28</td>
              <td>
                <p><span class="name"><a name="BASIC_REGS_REGMAP|GIT_HASH_REGISTER|GIT_CLEAN"></a>GIT_CLEAN</span><span class="attr"> </span></p>
                <p>0x0 in case the git status was clean<br>
          0xF in case there were uncommitted changes</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">27..0</td>
              <td>
                <p><span class="name"><a name="BASIC_REGS_REGMAP|GIT_HASH_REGISTER|GIT_HASH"></a>GIT_HASH</span><span class="attr"> </span></p>
                <p>7 hex digit hash code of the commit</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="BASIC_REGS_REGMAP|SLAVE_VARIANT"></a>
            
<h3 class="register">Offset 0x0014: SLAVE_VARIANT Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('BASIC_REGS_REGMAP|SLAVE_VARIANT_in')">(<span id="show_BASIC_REGS_REGMAP|SLAVE_VARIANT_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_BASIC_REGS_REGMAP|SLAVE_VARIANT_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|BASE_WINDOW_GPIO">GPIO_REGMAP|BASE_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">SLAVE_VARIANT</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0014</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000014

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|BASE_WINDOW_SPI">SPI_REGMAP|BASE_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000014

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value = 0x00000000
</p>

<p class="reg_info">This register is defined in HDL source file basic_regs.v.</p>

</div>

<div class="info">

Contains information pertaining the variant of the programmable.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..0</td>
              <td>
                <p><span class="name"><a name="BASIC_REGS_REGMAP|SLAVE_VARIANT|VARIANT_REG"></a>VARIANT_REG</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Returns the variant of the programmable based on the part vendor.
         MAX10 variants return 0x583033(ASCII for MAX), while the XO3 variant
         returns 0x584F33 (ASCII for XO3)</p>
            
              </td>
            </tr>
            
</table>

</div>

</div>

</div>

            <div class="regmap">
              <a name="DB_CONTROL_REGMAP"></a>
              <h1 class="regmap">DB_CONTROL_REGMAP</h1>
            
            <div class="group"><a name="DB_CONTROL_REGMAP|DB_CONTROL_WINDOWS"></a><h2 class="group">DB_CONTROL_WINDOWS</h2>
            Windows need to be without gaps to guarantee response to combiners.
            <div class="register">
              <a name="DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS"></a>
            
<h3 class="register">Offset 0x0000: ATR_CONTROLLER_REGS Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#ATR_REGMAP">ATR_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS_in')">(<span id="show_DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">ATR_CONTROLLER_REGS</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x20 (32 bytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001000

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001000

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">



</div>

</div>

            <div class="register">
              <a name="DB_CONTROL_REGMAP|LO_CONTROL_REGS"></a>
            
<h3 class="register">Offset 0x0020: LO_CONTROL_REGS Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#LO_CONTROL_REGMAP">LO_CONTROL_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('DB_CONTROL_REGMAP|LO_CONTROL_REGS_in')">(<span id="show_DB_CONTROL_REGMAP|LO_CONTROL_REGS_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DB_CONTROL_REGMAP|LO_CONTROL_REGS_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">LO_CONTROL_REGS</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0020</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x3E0 (992 bytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001020

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001020

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">

Extended original size of 0x20 to fill gap to next window.

</div>

</div>

            <div class="register">
              <a name="DB_CONTROL_REGMAP|LED_SETUP_REGS"></a>
            
<h3 class="register">Offset 0x0400: LED_SETUP_REGS Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#LED_SETUP_REGMAP">LED_SETUP_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('DB_CONTROL_REGMAP|LED_SETUP_REGS_in')">(<span id="show_DB_CONTROL_REGMAP|LED_SETUP_REGS_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DB_CONTROL_REGMAP|LED_SETUP_REGS_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">LED_SETUP_REGS</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0400</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0xC00 (3 Kbytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001400

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001400

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">

Extended original size of 0x400 to fill gap to next window.

</div>

</div>

            <div class="register">
              <a name="DB_CONTROL_REGMAP|SWITCH_SETUP_REGS"></a>
            
<h3 class="register">Offset 0x1000: SWITCH_SETUP_REGS Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#SWITCH_SETUP_REGMAP">SWITCH_SETUP_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('DB_CONTROL_REGMAP|SWITCH_SETUP_REGS_in')">(<span id="show_DB_CONTROL_REGMAP|SWITCH_SETUP_REGS_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DB_CONTROL_REGMAP|SWITCH_SETUP_REGS_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">SWITCH_SETUP_REGS</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x1000</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x1000 (4 Kbytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x002000

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x002000

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">



</div>

</div>

            <div class="register">
              <a name="DB_CONTROL_REGMAP|DSA_SETUP_REGS"></a>
            
<h3 class="register">Offset 0x2000: DSA_SETUP_REGS Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#DSA_SETUP_REGMAP">DSA_SETUP_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('DB_CONTROL_REGMAP|DSA_SETUP_REGS_in')">(<span id="show_DB_CONTROL_REGMAP|DSA_SETUP_REGS_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DB_CONTROL_REGMAP|DSA_SETUP_REGS_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">DSA_SETUP_REGS</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x2000</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x3000 (12 Kbytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x003000

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x003000

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">



</div>

</div>

</div>

            <div class="group"><a name="DB_CONTROL_REGMAP|REGISTER_ENDPOINTS"></a><h2 class="group">REGISTER_ENDPOINTS</h2>
            
            <div class="enum">
              <a name="DB_CONTROL_REGMAP|REGISTER_BLOCKS"></a>
            
<h3 class="enum">REGISTER_BLOCKS Enumeration</h3>

            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' > Value </td>
                    <td class="l"   colspan='1'> Name </td>
                    
</tr>

<tr valign="top">

                        <td class='value'>0</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='DB_CONTROL_REGMAP|REGISTER_BLOCKS|ATR_REGISTERS'></a>ATR_REGISTERS</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>1</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='DB_CONTROL_REGMAP|REGISTER_BLOCKS|LED_REGISTERS'></a>LED_REGISTERS</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>2</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='DB_CONTROL_REGMAP|REGISTER_BLOCKS|LO_SPI'></a>LO_SPI</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>3</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='DB_CONTROL_REGMAP|REGISTER_BLOCKS|SW_CONTROL'></a>SW_CONTROL</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>4</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='DB_CONTROL_REGMAP|REGISTER_BLOCKS|DSA_CONTROL'></a>DSA_CONTROL</p>
                            
</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file zbx_cpld_core.v.
                </p>
                
</div>

</div>

</div>

            <div class="regmap">
              <a name="DSA_SETUP_REGMAP"></a>
              <h1 class="regmap">DSA_SETUP_REGMAP</h1>
            <div class="xmlpmd">
</div>
            <div class="group"><a name="DSA_SETUP_REGMAP|DSA_SETUP_REGISTERS"></a><h2 class="group">DSA_SETUP_REGISTERS</h2>
            <div class="xmlpmd">
<p>The following registers control the digital step attenuators (DSA).</p>
<p>There are two ways to set the DSA values, which are applied to the DB ICs.</p>
<ol>
<li>
<p>The ...DSA_ATR registers can be used to access the raw
values of each ATR configuration.</p>
</li>
<li>
<p>Gain tables can be used as intermediate step to abstract from the
raw DB values. This gain table can be modified using the ...DSA_TABLE
registers according to the content of the registers from the first
option.  Initially each gain table is empty (all zeros). Each gain
table entry can be accessed at any time. Once the table is filled with
values the ...DSA_TABLE_SELECT registers can be used to get one gain
table entry with index TABLE_INDEX and write it to the appropriate ATR
configuration given by the address (see <em>show extended info</em> link below
the register array headlines)</p>
</li>
</ol></div>
            <div class="register">
              <a name="DSA_SETUP_REGMAP|TX0_DSA_ATR"></a>
            
<h3 class="register">Offset 0x0000: TX0_DSA_ATR(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|TX0_DSA_ATR_in')">(<span id="show_DSA_SETUP_REGMAP|TX0_DSA_ATR_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|TX0_DSA_ATR_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">TX0_DSA_ATR</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x003000 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x003000 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x00001F1F</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>TX_DSA_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Controls the Tx0 DSAs by accessing the raw attenuation levels.</p>
<p>This register array can hold settings for all ATR configurations.
The register index equals the ATR configuration.
The active configuration can be selected in <a href="#ATR_REGMAP">ATR_REGMAP</a>.
Independently all configurations can be read/written at any time.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..13</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">12..8</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|TX0_DSA_ATR|TX_DSA2"></a>TX_DSA2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=31)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..5</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">4..0</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|TX0_DSA_ATR|TX_DSA1"></a>TX_DSA1</span><span class="attr"> &nbsp;&nbsp;(initialvalue=31)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|TX1_DSA_ATR"></a>
            
<h3 class="register">Offset 0x0400: TX1_DSA_ATR(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|TX1_DSA_ATR_in')">(<span id="show_DSA_SETUP_REGMAP|TX1_DSA_ATR_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|TX1_DSA_ATR_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">TX1_DSA_ATR</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0400 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x003400 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x003400 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x00001F1F</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>TX_DSA_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Controls the Tx1 DSAs by accessing the raw attenuation levels.</p>
<p>This register array can hold settings for all ATR configurations.
The register index equals the ATR configuration.
The active configuration can be selected in <a href="#ATR_REGMAP">ATR_REGMAP</a>.
Independently all configurations can be read/written at any time.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..13</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">12..8</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|TX1_DSA_ATR|TX_DSA2"></a>TX_DSA2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=31)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..5</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">4..0</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|TX1_DSA_ATR|TX_DSA1"></a>TX_DSA1</span><span class="attr"> &nbsp;&nbsp;(initialvalue=31)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|RX0_DSA_ATR"></a>
            
<h3 class="register">Offset 0x0800: RX0_DSA_ATR(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|RX0_DSA_ATR_in')">(<span id="show_DSA_SETUP_REGMAP|RX0_DSA_ATR_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|RX0_DSA_ATR_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RX0_DSA_ATR</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0800 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x003800 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x003800 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x0000FFFF</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>RX_DSA_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Controls the Rx0 DSAs by accessing the raw attenuation levels.</p>
<p>This register array can hold settings for all ATR configurations.
The register index equals the ATR configuration.
The active configuration can be selected in <a href="#ATR_REGMAP">ATR_REGMAP</a>.
Independently all configurations can be read/written at any time.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..12</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX0_DSA_ATR|RX_DSA3_B"></a>RX_DSA3_B</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}</p></div></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">11..8</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX0_DSA_ATR|RX_DSA3_A"></a>RX_DSA3_A</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..4</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX0_DSA_ATR|RX_DSA2"></a>RX_DSA2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3..0</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX0_DSA_ATR|RX_DSA1"></a>RX_DSA1</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|RX1_DSA_ATR"></a>
            
<h3 class="register">Offset 0x0C00: RX1_DSA_ATR(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|RX1_DSA_ATR_in')">(<span id="show_DSA_SETUP_REGMAP|RX1_DSA_ATR_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|RX1_DSA_ATR_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RX1_DSA_ATR</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0C00 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x003C00 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x003C00 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x0000FFFF</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>RX_DSA_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Controls the Rx1 DSAs by accessing the raw attenuation levels.</p>
<p>This register array can hold settings for all ATR configurations.
The register index equals the ATR configuration.
The active configuration can be selected in <a href="#ATR_REGMAP">ATR_REGMAP</a>.
Independently all configurations can be read/written at any time.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..12</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX1_DSA_ATR|RX_DSA3_B"></a>RX_DSA3_B</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}</p></div></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">11..8</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX1_DSA_ATR|RX_DSA3_A"></a>RX_DSA3_A</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..4</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX1_DSA_ATR|RX_DSA2"></a>RX_DSA2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3..0</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX1_DSA_ATR|RX_DSA1"></a>RX_DSA1</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|TX0_DSA_TABLE_SELECT"></a>
            
<h3 class="register">Offset 0x1000: TX0_DSA_TABLE_SELECT(255:0) Register Array (W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|TX0_DSA_TABLE_SELECT_in')">(<span id="show_DSA_SETUP_REGMAP|TX0_DSA_TABLE_SELECT_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|TX0_DSA_TABLE_SELECT_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">TX0_DSA_TABLE_SELECT</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x1000 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x004000 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x004000 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>DSA_TABLE_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Controls the Tx0 DSAs by using the gain table to translate the table
index to raw attenuation levels. The register offset (i) is targeting
an ATR configuration to store the values from the gain table.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..8</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..0w</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|TX0_DSA_TABLE_SELECT|TABLE_INDEX"></a>TABLE_INDEX</span><span class="attr"> </span></p>
                <p><div class="xmlpmd">
<p>Gain table index to be used for getting the raw attenuation values.</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|TX1_DSA_TABLE_SELECT"></a>
            
<h3 class="register">Offset 0x1400: TX1_DSA_TABLE_SELECT(255:0) Register Array (W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|TX1_DSA_TABLE_SELECT_in')">(<span id="show_DSA_SETUP_REGMAP|TX1_DSA_TABLE_SELECT_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|TX1_DSA_TABLE_SELECT_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">TX1_DSA_TABLE_SELECT</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x1400 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x004400 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x004400 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>DSA_TABLE_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Controls the Tx1 DSAs by using the gain table to translate the table
index to raw attenuation levels. The register offset (i) is targeting
an ATR configuration to store the values from the gain table.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..8</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..0w</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|TX1_DSA_TABLE_SELECT|TABLE_INDEX"></a>TABLE_INDEX</span><span class="attr"> </span></p>
                <p><div class="xmlpmd">
<p>Gain table index to be used for getting the raw attenuation values.</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|RX0_DSA_TABLE_SELECT"></a>
            
<h3 class="register">Offset 0x1800: RX0_DSA_TABLE_SELECT(255:0) Register Array (W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|RX0_DSA_TABLE_SELECT_in')">(<span id="show_DSA_SETUP_REGMAP|RX0_DSA_TABLE_SELECT_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|RX0_DSA_TABLE_SELECT_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RX0_DSA_TABLE_SELECT</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x1800 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x004800 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x004800 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>DSA_TABLE_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Controls the Rx0 DSAs by using the gain table to translate the table
index to raw attenuation levels. The register offset (i) is targeting
an ATR configuration to store the values from the gain table.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..8</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..0w</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX0_DSA_TABLE_SELECT|TABLE_INDEX"></a>TABLE_INDEX</span><span class="attr"> </span></p>
                <p><div class="xmlpmd">
<p>Gain table index to be used for getting the raw attenuation values.</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|RX1_DSA_TABLE_SELECT"></a>
            
<h3 class="register">Offset 0x1C00: RX1_DSA_TABLE_SELECT(255:0) Register Array (W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|RX1_DSA_TABLE_SELECT_in')">(<span id="show_DSA_SETUP_REGMAP|RX1_DSA_TABLE_SELECT_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|RX1_DSA_TABLE_SELECT_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RX1_DSA_TABLE_SELECT</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x1C00 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x004C00 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x004C00 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>DSA_TABLE_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Controls the Rx1 DSAs by using the gain table to translate the table
index to raw attenuation levels. The register offset (i) is targeting
an ATR configuration to store the values from the gain table.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..8</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..0w</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX1_DSA_TABLE_SELECT|TABLE_INDEX"></a>TABLE_INDEX</span><span class="attr"> </span></p>
                <p><div class="xmlpmd">
<p>Gain table index to be used for getting the raw attenuation values.</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|TX0_DSA_TABLE"></a>
            
<h3 class="register">Offset 0x2000: TX0_DSA_TABLE(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|TX0_DSA_TABLE_in')">(<span id="show_DSA_SETUP_REGMAP|TX0_DSA_TABLE_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|TX0_DSA_TABLE_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">TX0_DSA_TABLE</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x2000 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x005000 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x005000 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x00001F1F</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>TX_DSA_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Provides access to the gain table for Tx0.</p>
<p>Each entry i will be saved in the gain table without any implications
on HW. Enables SW to use the table index in <a href="#DSA_SETUP_REGMAP|TX0_DSA_TABLE_SELECT">TX0_DSA_TABLE_SELECT</a> to
modify the ATR configurations.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..13</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">12..8</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|TX0_DSA_TABLE|TX_DSA2"></a>TX_DSA2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=31)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..5</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">4..0</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|TX0_DSA_TABLE|TX_DSA1"></a>TX_DSA1</span><span class="attr"> &nbsp;&nbsp;(initialvalue=31)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|TX1_DSA_TABLE"></a>
            
<h3 class="register">Offset 0x2400: TX1_DSA_TABLE(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|TX1_DSA_TABLE_in')">(<span id="show_DSA_SETUP_REGMAP|TX1_DSA_TABLE_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|TX1_DSA_TABLE_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">TX1_DSA_TABLE</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x2400 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x005400 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x005400 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x00001F1F</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>TX_DSA_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Provides access to the gain table for Tx1.</p>
<p>Each entry i will be saved in the gain table without any implications
on HW. Enables SW to use the table index in <a href="#DSA_SETUP_REGMAP|TX1_DSA_TABLE_SELECT">TX1_DSA_TABLE_SELECT</a> to
modify the ATR configurations.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..13</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">12..8</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|TX1_DSA_TABLE|TX_DSA2"></a>TX_DSA2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=31)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..5</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">4..0</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|TX1_DSA_TABLE|TX_DSA1"></a>TX_DSA1</span><span class="attr"> &nbsp;&nbsp;(initialvalue=31)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|RX0_DSA_TABLE"></a>
            
<h3 class="register">Offset 0x2800: RX0_DSA_TABLE(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|RX0_DSA_TABLE_in')">(<span id="show_DSA_SETUP_REGMAP|RX0_DSA_TABLE_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|RX0_DSA_TABLE_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RX0_DSA_TABLE</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x2800 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x005800 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x005800 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x0000FFFF</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>RX_DSA_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Provides access to the gain table for Rx0.</p>
<p>Each entry i will be saved in the gain table without any implications
on HW. Enables SW to use the table index in <a href="#DSA_SETUP_REGMAP|RX0_DSA_TABLE_SELECT">RX0_DSA_TABLE_SELECT</a> to
modify the ATR configurations.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..12</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX0_DSA_TABLE|RX_DSA3_B"></a>RX_DSA3_B</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}</p></div></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">11..8</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX0_DSA_TABLE|RX_DSA3_A"></a>RX_DSA3_A</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..4</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX0_DSA_TABLE|RX_DSA2"></a>RX_DSA2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3..0</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX0_DSA_TABLE|RX_DSA1"></a>RX_DSA1</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="DSA_SETUP_REGMAP|RX1_DSA_TABLE"></a>
            
<h3 class="register">Offset 0x2C00: RX1_DSA_TABLE(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('DSA_SETUP_REGMAP|RX1_DSA_TABLE_in')">(<span id="show_DSA_SETUP_REGMAP|RX1_DSA_TABLE_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_DSA_SETUP_REGMAP|RX1_DSA_TABLE_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|DSA_SETUP_REGS">DB_CONTROL_REGMAP|DSA_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RX1_DSA_TABLE</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x2C00 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x005C00 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x005C00 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x0000FFFF</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file dsa_control.v.<BR/>
It uses RegType <b>RX_DSA_CONTROL</b> which is defined in HDL source file dsa_control.v.</p>

</div>

<div class="info">

<div class="xmlpmd">
</div><BR/>
<div class="xmlpmd">
<p>Provides access to the gain table for Rx1.</p>
<p>Each entry i will be saved in the gain table without any implications
on HW. Enables SW to use the table index in <a href="#DSA_SETUP_REGMAP|RX1_DSA_TABLE_SELECT">RX1_DSA_TABLE_SELECT</a> to
modify the ATR configurations.</p></div>

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..12</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX1_DSA_TABLE|RX_DSA3_B"></a>RX_DSA3_B</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}</p></div></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">11..8</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX1_DSA_TABLE|RX_DSA3_A"></a>RX_DSA3_A</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..4</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX1_DSA_TABLE|RX_DSA2"></a>RX_DSA2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3..0</td>
              <td>
                <p><span class="name"><a name="DSA_SETUP_REGMAP|RX1_DSA_TABLE|RX_DSA1"></a>RX_DSA1</span><span class="attr"> &nbsp;&nbsp;(initialvalue=15)</span></p>
                <p><div class="xmlpmd">
<p>Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).</p></div></p>
            
              </td>
            </tr>
            
</table>

</div>

</div>

</div>

            <div class="regmap">
              <a name="GPIO_REGMAP"></a>
              <h1 class="regmap">GPIO_REGMAP</h1>
            
            <div class="group"><a name="GPIO_REGMAP|GPIO_REGMAP_WINDOWS"></a><h2 class="group">GPIO_REGMAP_WINDOWS</h2>
            
            <div class="register">
              <a name="GPIO_REGMAP|BASE_WINDOW_GPIO"></a>
            
<h3 class="register">Offset 0x0000: BASE_WINDOW_GPIO Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#BASIC_REGS_REGMAP">BASIC_REGS_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('GPIO_REGMAP|BASE_WINDOW_GPIO_in')">(<span id="show_GPIO_REGMAP|BASE_WINDOW_GPIO_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_GPIO_REGMAP|BASE_WINDOW_GPIO_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">BASE_WINDOW_GPIO</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x20 (32 bytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000000

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">



</div>

</div>

            <div class="register">
              <a name="GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO"></a>
            
<h3 class="register">Offset 0x1000: DB_CONTROL_WINDOW_GPIO Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#DB_CONTROL_REGMAP">DB_CONTROL_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO_in')">(<span id="show_GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">DB_CONTROL_WINDOW_GPIO</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x1000</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x5000 (20 Kbytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001000

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">



</div>

</div>

</div>

</div>

            <div class="regmap">
              <a name="LED_SETUP_REGMAP"></a>
              <h1 class="regmap">LED_SETUP_REGMAP</h1>
            
            <div class="group"><a name="LED_SETUP_REGMAP|LED_SETUP_REGISTERS"></a><h2 class="group">LED_SETUP_REGISTERS</h2>
            Contains registers that control the LEDs.
            <div class="register">
              <a name="LED_SETUP_REGMAP|LED_CONTROL"></a>
            
<h3 class="register">Offset 0x0000: LED_CONTROL(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('LED_SETUP_REGMAP|LED_CONTROL_in')">(<span id="show_LED_SETUP_REGMAP|LED_CONTROL_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_LED_SETUP_REGMAP|LED_CONTROL_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|LED_SETUP_REGS">DB_CONTROL_REGMAP|LED_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000400</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">LED_CONTROL</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001400 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001400 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x00000000</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file led_control.v.<BR/>
It uses RegType <b>LED_CONTROL_TYPE</b> which is defined in HDL source file led_control.v.</p>

</div>

<div class="info">

Defines LED functionality.<BR/>
This register array can hold settings for all ATR configurations.
        The register index equals the ATR configuration.
        The active configuration can be selected in <a href="#ATR_REGMAP">ATR_REGMAP</a>.
        Independently all configurations can be read/written at any time.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..19</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">18..17</td>
              <td>
                <p><span class="name"><a name="LED_SETUP_REGMAP|LED_CONTROL|CH1_TRX1_LED_EN"></a>CH1_TRX1_LED_EN</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>This bitfield controls the RG LED<BR/>
          Bit 15 controls the Ch1 Rx Green LED<BR/>
          Bit 14 controls the Ch1 Tx Red LED<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">16</td>
              <td>
                <p><span class="name"><a name="LED_SETUP_REGMAP|LED_CONTROL|CH1_RX2_LED_EN"></a>CH1_RX2_LED_EN</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Enables the Ch1 Rx2 Green LED</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..8</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..3</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">2..1</td>
              <td>
                <p><span class="name"><a name="LED_SETUP_REGMAP|LED_CONTROL|CH0_TRX1_LED_EN"></a>CH0_TRX1_LED_EN</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>This bitfield controls the RG LED<BR/>
          Bit 6 controls the Ch0 Rx Green LED<BR/>
          Bit 7 controls the Ch0 Tx Red LED<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">0</td>
              <td>
                <p><span class="name"><a name="LED_SETUP_REGMAP|LED_CONTROL|CH0_RX2_LED_EN"></a>CH0_RX2_LED_EN</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Enables the Ch0 Rx2 Green LED</p>
            
              </td>
            </tr>
            
</table>

</div>

</div>

</div>

            <div class="regmap">
              <a name="LO_CONTROL_REGMAP"></a>
              <h1 class="regmap">LO_CONTROL_REGMAP</h1>
            
            <div class="group"><a name="LO_CONTROL_REGMAP|LO_SPI_REGISTERS"></a><h2 class="group">LO_SPI_REGISTERS</h2>
            Controls the SPI transaction to the LMX2572
            <div class="enum">
              <a name="LO_CONTROL_REGMAP|LO_CHIP_SELECT"></a>
            
<h3 class="enum">LO_CHIP_SELECT Enumeration</h3>

            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' > Value </td>
                    <td class="l"   colspan='1'> Name </td>
                    
</tr>

<tr valign="top">

                        <td class='value'>0</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX0_LO1'></a>TX0_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>1</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX0_LO2'></a>TX0_LO2</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>2</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX1_LO1'></a>TX1_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>3</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX1_LO2'></a>TX1_LO2</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>4</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX0_LO1'></a>RX0_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>5</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX0_LO2'></a>RX0_LO2</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>6</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX1_LO1'></a>RX1_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>7</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX1_LO2'></a>RX1_LO2</p>
                            
</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file lo_control.v.
                </p>
                
</div>

            <div class="register">
              <a name="LO_CONTROL_REGMAP|LO_SPI_SETUP"></a>
            
<h3 class="register">Offset 0x0000: LO_SPI_SETUP Register (W)</h3>

                 <a class="sh_addrs" href="javascript:sa('LO_CONTROL_REGMAP|LO_SPI_SETUP_in')">(<span id="show_LO_CONTROL_REGMAP|LO_SPI_SETUP_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_LO_CONTROL_REGMAP|LO_SPI_SETUP_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|LO_CONTROL_REGS">DB_CONTROL_REGMAP|LO_CONTROL_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000020</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">LO_SPI_SETUP</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001020

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001020

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value = 0x00000000
</p>

<p class="reg_info">This register is defined in HDL source file lo_control.v.</p>

</div>

<div class="info">

This register sets up the SPI transaction to read/write to/from to the LMX2572.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..29</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">28w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SPI_START_TRANSACTION"></a>LO_SPI_START_TRANSACTION</span><span class="attr"> &nbsp;&nbsp;(Strobe, initialvalue=0)</span></p>
                <p>Strobe this bit high to start the SPI transaction with the bitfields below</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">27</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">26..24w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SELECT"></a>LO_SELECT</span><span class="attr"> &nbsp;&nbsp;(Strobe, initialvalue=TX0_LO1)</span></p>
                <p>Sets the CS to the selected LO. The CS will assert until after <a href="#LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SPI_START_TRANSACTION">LO_SPI_START_TRANSACTION</a> has been asserted.</p>
            
                    <p>
                      The values for this bitfield are in the <a href="#LO_CONTROL_REGMAP|LO_CHIP_SELECT">LO_CHIP_SELECT</a> table.
                      <a class="sh_enum" href="javascript:sb('LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SELECT')">(<span id="show_LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SELECT">show here</span>)</a>
                    </p>
                    <div class="sh_enum" id="div_LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SELECT">
                    
            <div class="enum">
              <a name="LO_CONTROL_REGMAP|LO_CHIP_SELECT"></a>
            
            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' > Value </td>
                    <td class="l"   colspan='1'> Name </td>
                    
</tr>

<tr valign="top">

                        <td class='value'>0</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX0_LO1'></a>TX0_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>1</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX0_LO2'></a>TX0_LO2</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>2</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX1_LO1'></a>TX1_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>3</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX1_LO2'></a>TX1_LO2</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>4</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX0_LO1'></a>RX0_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>5</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX0_LO2'></a>RX0_LO2</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>6</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX1_LO1'></a>RX1_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>7</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX1_LO2'></a>RX1_LO2</p>
                            
</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file lo_control.v.
                </p>
                
</div>

</div>

              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SPI_RD"></a>LO_SPI_RD</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Set this bit to '1' to read from the LMX2572. Set this bit to '0' to write to the LMX2572.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">22..16w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SPI_WT_ADDR"></a>LO_SPI_WT_ADDR</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>7 bit address of the LMX2572</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..0w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SPI_WT_DATA"></a>LO_SPI_WT_DATA</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Write Data to the LMX2572</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="LO_CONTROL_REGMAP|LO_SPI_STATUS"></a>
            
<h3 class="register">Offset 0x0000: LO_SPI_STATUS Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('LO_CONTROL_REGMAP|LO_SPI_STATUS_in')">(<span id="show_LO_CONTROL_REGMAP|LO_SPI_STATUS_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_LO_CONTROL_REGMAP|LO_SPI_STATUS_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|LO_CONTROL_REGS">DB_CONTROL_REGMAP|LO_CONTROL_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000020</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">LO_SPI_STATUS</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001020

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001020

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value = 0x00000000
</p>

<p class="reg_info">This register is defined in HDL source file lo_control.v.</p>

</div>

<div class="info">

This register returns the SPI master status, and also returns the read data from the LMX2572

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_SPI_STATUS|LO_SPI_DATA_VALID"></a>LO_SPI_DATA_VALID</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Returns '1' when a read SPI transaction is complete. This bit will remain high until a new SPI transaction has started.
           i.e. <a href="#LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SPI_START_TRANSACTION">LO_SPI_START_TRANSACTION</a> is strobed. Poll this when expecting data from a read transaction.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">30</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_SPI_STATUS|LO_SPI_READY"></a>LO_SPI_READY</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>If this bit returns '1' then LMX2572 is ready for transaction. If it returns '0' then it is busy with a previous SPI transaction.
           Poll this bit before starting a SPI transaction.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">29..27</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">26..24</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_SPI_STATUS|LO_SELECT_STATUS"></a>LO_SELECT_STATUS</span><span class="attr"> &nbsp;&nbsp;(initialvalue=TX0_LO1)</span></p>
                <p>Returns the current selected CS. This bitfield will return the value written to <a href="#LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SELECT">LO_SELECT</a> bitfield in the <a href="#LO_CONTROL_REGMAP|LO_SPI_SETUP">LO_SPI_SETUP</a> reg.</p>
            
                    <p>
                      The values for this bitfield are in the <a href="#LO_CONTROL_REGMAP|LO_CHIP_SELECT">LO_CHIP_SELECT</a> table.
                      <a class="sh_enum" href="javascript:sb('LO_CONTROL_REGMAP|LO_SPI_STATUS|LO_SELECT_STATUS')">(<span id="show_LO_CONTROL_REGMAP|LO_SPI_STATUS|LO_SELECT_STATUS">show here</span>)</a>
                    </p>
                    <div class="sh_enum" id="div_LO_CONTROL_REGMAP|LO_SPI_STATUS|LO_SELECT_STATUS">
                    
            <div class="enum">
              <a name="LO_CONTROL_REGMAP|LO_CHIP_SELECT"></a>
            
            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' > Value </td>
                    <td class="l"   colspan='1'> Name </td>
                    
</tr>

<tr valign="top">

                        <td class='value'>0</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX0_LO1'></a>TX0_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>1</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX0_LO2'></a>TX0_LO2</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>2</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX1_LO1'></a>TX1_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>3</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|TX1_LO2'></a>TX1_LO2</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>4</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX0_LO1'></a>RX0_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>5</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX0_LO2'></a>RX0_LO2</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>6</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX1_LO1'></a>RX1_LO1</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>7</td>
                        
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='LO_CONTROL_REGMAP|LO_CHIP_SELECT|RX1_LO2'></a>RX1_LO2</p>
                            
</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file lo_control.v.
                </p>
                
</div>

</div>

              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">22..16</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_SPI_STATUS|LO_SPI_RD_ADDR"></a>LO_SPI_RD_ADDR</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Returns the address of the current SPI address setup</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..0</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_SPI_STATUS|LO_SPI_RD_DATA"></a>LO_SPI_RD_DATA</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Returns the data of the SPI read. This bitfield will return 0x0000 until <a href="#LO_CONTROL_REGMAP|LO_SPI_STATUS|LO_SPI_DATA_VALID">LO_SPI_DATA_VALID</a> is true. This bit field will maintain it's
           read value until a new SPI transaction has started. i.e. <a href="#LO_CONTROL_REGMAP|LO_SPI_SETUP|LO_SPI_START_TRANSACTION">LO_SPI_START_TRANSACTION</a> is strobed.</p>
            
              </td>
            </tr>
            
</table>

</div>

</div>

            <div class="group"><a name="LO_CONTROL_REGMAP|LO_SYNC_REGS"></a><h2 class="group">LO_SYNC_REGS</h2>
            Contains registers that control the logic lines in charge of synchronization
            <div class="register">
              <a name="LO_CONTROL_REGMAP|LO_PULSE_SYNC"></a>
            
<h3 class="register">Offset 0x0004: LO_PULSE_SYNC Register (W)</h3>

                 <a class="sh_addrs" href="javascript:sa('LO_CONTROL_REGMAP|LO_PULSE_SYNC_in')">(<span id="show_LO_CONTROL_REGMAP|LO_PULSE_SYNC_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_LO_CONTROL_REGMAP|LO_PULSE_SYNC_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|LO_CONTROL_REGS">DB_CONTROL_REGMAP|LO_CONTROL_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000020</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">LO_PULSE_SYNC</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0004</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001024

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001024

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value = 0x00000000
</p>

<p class="reg_info">This register is defined in HDL source file lo_control.v.</p>

</div>

<div class="info">

Controls pulses driven to the SYNC pins of the LMX2572 chips

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..9</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">8w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_PULSE_SYNC|BYPASS_SYNC_REGISTER"></a>BYPASS_SYNC_REGISTER</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Setting this bit to '1' will ignore writes to the PULSE_X_SYNC fields and allow
           a buffered input SYNC pulse to be driven out instead.</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_PULSE_SYNC|PULSE_RX1_LO2_SYNC"></a>PULSE_RX1_LO2_SYNC</span><span class="attr"> &nbsp;&nbsp;(Strobe, initialvalue=0)</span></p>
                <p>Creates a single cycle pulse on the RX1_LO2_SYNC line.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">6w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_PULSE_SYNC|PULSE_RX1_LO1_SYNC"></a>PULSE_RX1_LO1_SYNC</span><span class="attr"> &nbsp;&nbsp;(Strobe, initialvalue=0)</span></p>
                <p>Creates a single cycle pulse on the RX1_LO1_SYNC line.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">5w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_PULSE_SYNC|PULSE_RX0_LO2_SYNC"></a>PULSE_RX0_LO2_SYNC</span><span class="attr"> &nbsp;&nbsp;(Strobe, initialvalue=0)</span></p>
                <p>Creates a single cycle pulse on the RX0_LO2_SYNC line.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">4w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_PULSE_SYNC|PULSE_RX0_LO1_SYNC"></a>PULSE_RX0_LO1_SYNC</span><span class="attr"> &nbsp;&nbsp;(Strobe, initialvalue=0)</span></p>
                <p>Creates a single cycle pulse on the RX0_LO1_SYNC line.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_PULSE_SYNC|PULSE_TX1_LO2_SYNC"></a>PULSE_TX1_LO2_SYNC</span><span class="attr"> &nbsp;&nbsp;(Strobe, initialvalue=0)</span></p>
                <p>Creates a single cycle pulse on the TX1_LO2_SYNC line.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">2w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_PULSE_SYNC|PULSE_TX1_LO1_SYNC"></a>PULSE_TX1_LO1_SYNC</span><span class="attr"> &nbsp;&nbsp;(Strobe, initialvalue=0)</span></p>
                <p>Creates a single cycle pulse on the TX1_LO1_SYNC line.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">1w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_PULSE_SYNC|PULSE_TX0_LO2_SYNC"></a>PULSE_TX0_LO2_SYNC</span><span class="attr"> &nbsp;&nbsp;(Strobe, initialvalue=0)</span></p>
                <p>Creates a single cycle pulse on the TX0_LO2_SYNC line.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">0w</td>
              <td>
                <p><span class="name"><a name="LO_CONTROL_REGMAP|LO_PULSE_SYNC|PULSE_TX0_LO1_SYNC"></a>PULSE_TX0_LO1_SYNC</span><span class="attr"> &nbsp;&nbsp;(Strobe, initialvalue=0)</span></p>
                <p>Creates a single cycle pulse on the TX0_LO1_SYNC line.</p>
            
              </td>
            </tr>
            
</table>

</div>

</div>

</div>

            <div class="regmap">
              <a name="POWER_REGS_REGMAP"></a>
              <h1 class="regmap">POWER_REGS_REGMAP</h1>
            <p>This regmap has readablestrobes="true", so all strobe bits are readable by
default. This attribute should only be used for older regmaps to maintain
compatibility with previous versions of XmlParse. New regmaps should either
use the 'clearable' attribute or should explicitly define readable bits
in the same bit position as the strobe bits.</p>

            <div class="group"><a name="POWER_REGS_REGMAP|POWER_REGS_REGISTERS"></a><h2 class="group">POWER_REGS_REGISTERS</h2>
            This regmap contains the registers to control the power supplies and the clock buffer for PLL reference clock.
            <div class="register">
              <a name="POWER_REGS_REGMAP|RF_POWER_CONTROL"></a>
            
<h3 class="register">Offset 0x0000: RF_POWER_CONTROL Register (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('POWER_REGS_REGMAP|RF_POWER_CONTROL_in')">(<span id="show_POWER_REGS_REGMAP|RF_POWER_CONTROL_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_POWER_REGS_REGMAP|RF_POWER_CONTROL_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|POWER_REGS">SPI_REGMAP|POWER_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000040</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RF_POWER_CONTROL</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000040

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value = 0x00000000
</p>

<p class="reg_info">This register is defined in HDL source file power_regs.v.</p>

</div>

<div class="info">

This register controls power supply enables to the Tx/Rx amps, switch control, and clk buffers. During normal
       operations, all three power supplies should be enabled.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..8</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..3</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">2</td>
              <td>
                <p><span class="name"><a name="POWER_REGS_REGMAP|RF_POWER_CONTROL|ENABLE_3v3"></a>ENABLE_3v3</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>This power supply sources the switch control, and the clock buffers. By default this power supply is off.
         The internal LOs will not work unless this bit is enabled.<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">1</td>
              <td>
                <p><span class="name"><a name="POWER_REGS_REGMAP|RF_POWER_CONTROL|ENABLE_RX_7V0"></a>ENABLE_RX_7V0</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>This power supply sources the Rx0 and Rx1 amps. By default this power supply is off.The Rx0/1 path will not
         be active unless this power supply is enabled. Disabling this bit is similar to RX RF blanking<BR/>
         <font color="red">note to digital engineer, this is Pos7v0B</font></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">0</td>
              <td>
                <p><span class="name"><a name="POWER_REGS_REGMAP|RF_POWER_CONTROL|ENABLE_TX_7V0"></a>ENABLE_TX_7V0</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>This power supply sources the Tx0 and Tx1 amps. By default this power supply is off. The Tx0/1 path will not
         be active unless this power supply is enabled. Disabling this bit is similar to TX RF blanking<BR/>
         <font color="red">note to digital engineer, this is Pos7v0A</font></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="POWER_REGS_REGMAP|RF_POWER_STATUS"></a>
            
<h3 class="register">Offset 0x0004: RF_POWER_STATUS Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('POWER_REGS_REGMAP|RF_POWER_STATUS_in')">(<span id="show_POWER_REGS_REGMAP|RF_POWER_STATUS_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_POWER_REGS_REGMAP|RF_POWER_STATUS_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|POWER_REGS">SPI_REGMAP|POWER_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000040</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RF_POWER_STATUS</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0004</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000044

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file power_regs.v.</p>

</div>

<div class="info">

Returns status of PowerGood indicators across the daughterboard.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..8</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..2</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">1</td>
              <td>
                <p><span class="name"><a name="POWER_REGS_REGMAP|RF_POWER_STATUS|P7V_B_STATUS"></a>P7V_B_STATUS</span><span class="attr"> </span></p>
                <p>Returns status of 7V switching regulator B.<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">0</td>
              <td>
                <p><span class="name"><a name="POWER_REGS_REGMAP|RF_POWER_STATUS|P7V_A_STATUS"></a>P7V_A_STATUS</span><span class="attr"> </span></p>
                <p>Returns status of 7V switching regulator A.<BR/></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="POWER_REGS_REGMAP|PRC_CONTROL"></a>
            
<h3 class="register">Offset 0x0008: PRC_CONTROL Register (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('POWER_REGS_REGMAP|PRC_CONTROL_in')">(<span id="show_POWER_REGS_REGMAP|PRC_CONTROL_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_POWER_REGS_REGMAP|PRC_CONTROL_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|POWER_REGS">SPI_REGMAP|POWER_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000040</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">PRC_CONTROL</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0008</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000048

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value = 0x00000000
</p>

<p class="reg_info">This register is defined in HDL source file power_regs.v.</p>

</div>

<div class="info">

Offers ability to enable or disable the PLL reference clock.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..8</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..1</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">0</td>
              <td>
                <p><span class="name"><a name="POWER_REGS_REGMAP|PRC_CONTROL|PLL_REF_CLOCK_ENABLE"></a>PLL_REF_CLOCK_ENABLE</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>If set PLL reference clock is enabled.</p>
            
              </td>
            </tr>
            
</table>

</div>

</div>

</div>

            <div class="regmap">
              <a name="RECONFIG_REGMAP"></a>
              <h1 class="regmap">RECONFIG_REGMAP</h1>
            
            <div class="group"><a name="RECONFIG_REGMAP|RECONFIG_REGS"></a><h2 class="group">RECONFIG_REGS</h2>
            These registers are used to upload and verify a new primary image to the
    Max 10 FPGA on-chip flash when configured to support dual configuration
    images. The steps below outline the process of verifying/preparing the
    new image to be written, erasing the current image, writing the new
    image, and verifying the new image was successfully written.
      <p><b>Prepare the data...</b>
            <ol><li><p>The Max 10 FPGA build should generate a *cfm0_auto.rpd
                    file The *.rpd file is a "raw programming
                    data" file holding all data related to the
                    configuration image (CFM0). There are two
                    important items to note regarding the addresses.
                    First the *rpd data uses <b>byte</b> addresses.
                    Second, the start/end addresses defined by
                    FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses</p></li>
                <li><p>As a sanity check, verify the size of the raw
                    programming data for CFM0 correspond to the address
                    range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by
                    reading the values from FLASH_CFM0_START_ADDR_REG and
                    FLASH_CFM0_END_ADDR, subtract both values, add one and
                    multiply by four.
                    </p></li>
                <li><p>Having passed the sanity check the *.rpd data must
                    now be manipulated into the form required by Altera's
                    on-chip flash IP. Two operations must be performed.
                    First the data must be converted from bytes to 32-bit
                    words. Second the bit order must be reversed. This is
                    illustrated in in the following table which shows byte
                    address and data from the *.rpd file compared to the
                    word address and data to be written to the on-chip
                    flash.
                    <table border=1>
                      <tr><td>.Map Addr</td><td>.Map Data</td><td>Flash Addr</td><td>Flash Data</td></tr>
                      <tr><td>0x2B800</td><td>0x01</td><td rowspan=4>0xAC00</td><td rowspan=4>0x8040C020</td></tr>
                      <tr><td>0x2B801</td><td>0x02</td></tr>
                      <tr><td>0x2B802</td><td>0x03</td></tr>
                      <tr><td>0x2B803</td><td>0x04</td></tr>
                      <tr><td>0x2B804</td><td>0x05</td><td rowspan=4>0xAC01</td><td rowspan=4>0xA060E010</td></tr>
                      <tr><td>0x2B805</td><td>0x06</td></tr>
                      <tr><td>0x2B806</td><td>0x07</td></tr>
                      <tr><td>0x2B807</td><td>0x08</td></tr>
                    </table>
                    </p></li>
                <li><p>The resulting set of flash address data pairs should
                    be used when writing FLASH_ADDR_REG and
                    FLASH_WRITE_DATA_REG to update the CFM0 image.
                    However, prior to writing the new image the old image
                    must be erased.
                    </p></li>
            </ol>
      </p>
      <p><b>Erase the current primary flash image...</b>
            <ol><p><li>Read FLASH_STATUS_REG and verify no error bits are
                    asserted and that all read, write, and erase operations
                    are idle.</p></li>
                <p><li>Disable write protection of the flash by strobing the
                    FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG.
                    </p></li>
                <p><li>Verify write protection is disabled and no errors are
                    present by reading FLASH_STATUS_REG.</p></li>
                <p><li>Initiate the erase operation by setting
                    <a href="#RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_SECTOR">FLASH_ERASE_SECTOR</a> and strobing FLASH_ERASE_STB of
                    FLASH_CONTROL_REG.</p></li>
                <p><li>Poll the FLASH_ERASE_IDLE bit of
                    FLASH_STATUS_REG until it de-asserts indicating the
                    erase operation is complete, then verify the operation
                    was successful by checking that the FLASH_ERASE_ERR
                    bit is de-asserted. Erase operations are expected to
                    take a maximum of 350 msec. Upon completion of the erase
                    operation write protection will remain disabled.
                    </p></li>
                <p><li>Erase additional sectors as required (see
                    <a href="#RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_SECTOR">FLASH_ERASE_SECTOR</a> for details) by restarting with first
                    step.</p></li>
            </ol>
      </p>
      <p><b>Write the new primary flash image...</b>
            <ol><p><li>Read FLASH_STATUS_REG and verify no error bits are
                    asserted, all read, write, and erase operations are
                    idle, and write protection is disabled.</li>
                <p><li>Set the target address for the write to the Max 10
                    on-chip flash by writing value from
                    FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.</li></p>
                <p><li>Set the data to be written to this address by writing
                    the new 32-bit word of the new image to
                    FLASH_WRITE_DATA_REG.</li></p>
                <p><li>Initiate the write by strobing FLASH_WRITE_STB of
                    FLASH_CONTROL_REG.</li></p>
                <p><li>Poll the FLASH_WRITE_IDLE bit of
                    FLASH_STATUS_REG until it de-asserts indicating the
                    write operation is complete, then verify the operation
                    was successful by checking that the FLASH_WRITE_ERR
                    bit is de-asserted. Write operations are expected to
                    take a maximum of 550 usec.</li></p>
                <p><li>Upon completion of the write operation return to step
                     2, incrementing the target address by one, and writing
                     the next 32-bit word to Max10FlashWriteDatReg. If this
                     was the last write, indicated by writing to
                     FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step
                     to enable write protection.</li></p>
                <p><li>After writing the new image enable write protection
                     by strobing the FLASH_ENABLE_WP_STB bit of
                     FLASH_CONTROL_REG.</li></p>
            </ol>
      </p>
      <p><b>Verify the new primary flash image...</b>
            <ol><p><li>Read FLASH_STATUS_REG and verify no error bits are
                    asserted and that all read, write, and erase operations
                    are idle.</li></p>
                <p><li>Set the target address for the read in the Max 10
                    on-chip flash by writing value from
                    FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.</li></p>
                <p><li>Initiate the read by strobing FLASH_READ_STB of
                    FLASH_CONTROL_REG.</li></p>
                <p><li>Poll the FLASH_READ_IDLE bit of
                    FLASH_STATUS_REG until it de-asserts indicating the
                    read operation is complete, then verify the operation
                    was successful by checking that the FLASH_READ_ERR
                    bit is de-asserted. There is no guidance on exactly how
                    long reads take to complete, but they are expected to be
                    fairly quick. A very conservative timeout on this
                    polling would be similar to that used for write
                    operations.</li></p>
                 <p><li>Upon completion of the read operation the resulting
                     data returned by the on-chip flash will be available in
                     Max10FlashReadDatReg. Read this register, compare to
                     expected value previously written, and ensure they
                     match.</li></p>
                 <p><li>Return to step 2, incrementing the target
                     address by one. If this was the last read verification
                     is complete and no further action is required.</li></p>
            </ol>
      </p>
      <p>After the flash has been erased, programmed, and verified, a power
         cycle is required for the new image to become active.
      </p>
            <div class="enum">
              <a name="RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM"></a>
            
<h3 class="enum">FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration</h3>
These values are the start and end address of the CFM image flash
        sector from Intel's On-Chip Flash IP Generator.
        Be aware that three different values exist per each of the two
        supported MAX10 variants: 10M04 and 10M08
        Note that the values given in the IP generator are byte based where
        the values of this enum are U32 based (divided by 4).
            <table class="enum" border="0" cellspacing="0" cellpadding="0">
              <tr class="header" valign="center">
            
                    <td class='value' colspan='2'> Value </td>
                    <td class="l"  rowspan='2' colspan='1'> Name </td>
                    
</tr>

<tr class="header2" valign="bottom">

<td class='value'> Dec </td>

<td class='l'> Hex </td>

</tr>

<tr valign="top">

                        <td class='value'>4096</td>
                        
                            <td class='l'>0x01000</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>8192</td>
                        
                            <td class='l'>0x02000</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>39936</td>
                        
                            <td class='l'>0x09C00</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M04</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>44032</td>
                        
                            <td class='l'>0x0AC00</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M08</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>75775</td>
                        
                            <td class='l'>0x127FF</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M04</p>
                            
</td>

</tr>

<tr valign="top">

                        <td class='value'>79871</td>
                        
                            <td class='l'>0x137FF</td>
                            
                            <td class="l" style="text-align: left;">
                              <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M08</p>
                            
</td>

</tr>

</table>

                <p class="enum_info">
                  This enumerated type is defined in HDL source file reconfig_engine.v.
                </p>
                
</div>

            <div class="register">
              <a name="RECONFIG_REGMAP|FLASH_STATUS_REG"></a>
            
<h3 class="register">Offset 0x0000: FLASH_STATUS_REG Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_STATUS_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_STATUS_REG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_STATUS_REG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|RECONFIG">SPI_REGMAP|RECONFIG</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000020</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">FLASH_STATUS_REG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000020

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>

</div>

<div class="info">



</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..17</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">16</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED"></a>FLASH_MEM_INIT_ENABLED</span><span class="attr"> </span></p>
                <p>This bit is asserted when the flash can hold an image with memory
        initialization.</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..14</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">13</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_WRITE_ERR"></a>FLASH_WRITE_ERR</span><span class="attr"> </span></p>
                <p>This bit is asserted when write operation fails. Clear this error
          by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In
          the event of a write error...
          <li><b>the primary configuration image may be corrupted,</b> and
          power cycling the board may result unknown behavior.</li>
          <li>write protection of the flash will automatically be
          re-enabled.</li>
          <li>attempts to disable write protection will be ignored.</li>
          <li>attempts to read/write/erase the flash will be ignored.</li></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">12</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_WRITE_IDLE"></a>FLASH_WRITE_IDLE</span><span class="attr"> </span></p>
                <p>This bit is de-asserted when a write operation is in progress. Poll
        this bit after strobing the FLASH_WRITE_STB bit of
        FLASH_CONTROL_REG to determine when the write operation has
        completed, then check the FLASH_WRITE_ERR bit to verify the
        operation was successful.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">11..10</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">9</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_ERASE_ERR"></a>FLASH_ERASE_ERR</span><span class="attr"> </span></p>
                <p>This bit is asserted when an erase operation fails. Clear this
          error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In
          the event of an erase error...
          <li><b>the primary configuration image may be corrupted,</b> and
          power cycling the board may result in unknown behavior.</li>
          <li>write protection of the flash will automatically be
          re-enabled.</li>
         <li>attempts to disable write protection will be ignored.</li>
         <li>attempts to read/write/erase the flash will be ignored.</li></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">8</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_ERASE_IDLE"></a>FLASH_ERASE_IDLE</span><span class="attr"> </span></p>
                <p>This bit is de-asserted when an erase operation is in progress. Poll
        this bit after strobing the FLASH_ERASE_STB bit of
        FLASH_CONTROL_REG to determine when the erase operation has
        completed, then check the FLASH_ERASE_ERR bit to verify the
        operation was successful.</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..6</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">5</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_READ_ERR"></a>FLASH_READ_ERR</span><span class="attr"> </span></p>
                <p>This bit is asserted when a read operation fails. Clear this error
          by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the
          event of a read error...
          <li>the data in FLASH_READ_DATA_REG is invalid.</li>
          <li>attempts to disable write protection will be ignored.</li>
          <li>attempts to read/write/erase the flash will be ignored.</li></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">4</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_READ_IDLE"></a>FLASH_READ_IDLE</span><span class="attr"> </span></p>
                <p>This bit is de-asserted when a read operation is in progress. Poll
        this bit after strobing the FLASH_READ_STB bit of
        FLASH_CONTROL_REG to determine when the read operation has
        completed, then check the FLASH_READ_ERR bit to verify the
        operation was successful.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3..1</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">0</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_WP_ENABLED"></a>FLASH_WP_ENABLED</span><span class="attr"> </span></p>
                <p>This bit is asserted when the flash is write protected and
        de-asserted when write protection is disabled.
        <li>Write protection must be enabled prior to performing read
        operations.</li>
        <li>Write protection must be disabled prior to performing write and
        erase operations.</li></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="RECONFIG_REGMAP|FLASH_CONTROL_REG"></a>
            
<h3 class="register">Offset 0x0004: FLASH_CONTROL_REG Register (W)</h3>

                 <a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_CONTROL_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_CONTROL_REG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_CONTROL_REG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|RECONFIG">SPI_REGMAP|RECONFIG</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000020</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">FLASH_CONTROL_REG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0004</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000024

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>

</div>

<div class="info">



</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..16</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15..11</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">10w</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|CLEAR_FLASH_ERASE_ERROR_STB"></a>CLEAR_FLASH_ERASE_ERROR_STB</span><span class="attr"> &nbsp;&nbsp;(Strobe)</span></p>
                <p>Strobe this bit to clear an erase error.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">9w</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|CLEAR_FLASH_WRITE_ERROR_STB"></a>CLEAR_FLASH_WRITE_ERROR_STB</span><span class="attr"> &nbsp;&nbsp;(Strobe)</span></p>
                <p>Strobe this bit to clear a write error.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">8w</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|CLEAR_FLASH_READ_ERROR_STB"></a>CLEAR_FLASH_READ_ERROR_STB</span><span class="attr"> &nbsp;&nbsp;(Strobe)</span></p>
                <p>Strobe this bit to clear a read error.</p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..5w</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_SECTOR"></a>FLASH_ERASE_SECTOR</span><span class="attr"> &nbsp;&nbsp;(Strobe)</span></p>
                <p>Defines the sector to be erased. Has to be set latest with the
          write access which starts the erase operation by strobing
          <a href="#RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_STB">FLASH_ERASE_STB</a>.<br>
          With 10M04 variants, if the flash is configured to support memory
          initialization (see <a href="#RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED">FLASH_MEM_INIT_ENABLED</a> flag) the sectors 2
          to 4 have to be erased. If the flag is not asserted only sector 4
          has to be erased.
          With 10M08 variants, the sectors to be erased are 3 to 5 when
          using memory initialization or only sector 5 otherwise.</p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">4w</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_STB"></a>FLASH_ERASE_STB</span><span class="attr"> &nbsp;&nbsp;(Strobe)</span></p>
                <p>Strobe this bit to erase the primary Max10 configuration image
          (CFM0).
          <li>Prior to strobing this bit verify no other write or erase
          operations are in progress, write protection is disabled, and no
          error bits are asserted by reading FLASH_STATUS_REG.</li>
          <li>Attempts to erase the primary image while other write or erase
          operations are in progress will be ignored.
          <li>Attempts to erase the primary image when write protection is
          enabled will be ignored.</li>
          <li>Strobing this bit and FLASH_WRITE_STB simultaneously will
          result both the erase and the write operation being ignored, both
          corresponding error bits being set, and write protection being
          re-enabled.</li>
          <li>After strobing this bit poll the FLASH_ERASE_IDLE and
          FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when
          the erase operation is complete and if it was successful.</li></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3w</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_WRITE_STB"></a>FLASH_WRITE_STB</span><span class="attr"> &nbsp;&nbsp;(Strobe)</span></p>
                <p>Strobe this bit to write the data contained in
          FLASH_WRITE_DATA_REG to the flash address identified in
          FLASH_ADDR_REG.
          <li>The flash must be erased before writing new data.</li>
          <li>Prior to strobing this bit verify write protection is
          disabled, no other write or erase operations are in progress, and
          no error bits are asserted by reading FLASH_STATUS_REG.</li>
          <li>Attempts to write data while other write or erase operations
          are in progress will be ignored.</li>
          <li>Attempts to write data with write protection enabled will be
          ignored.</li>
          <li>Strobing this bit and FLASH_ERASE_STB simultaneously will
          result in both the write and erase operation being ignored,
          both corresponding error bits being set, and write protection
          being re-enabled.</li>
          <li>After strobing this bit poll theMax10FlashWriteIdle and
          FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when
          the write operation is complete and if it was successful.</li></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">2w</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_READ_STB"></a>FLASH_READ_STB</span><span class="attr"> &nbsp;&nbsp;(Strobe)</span></p>
                <p>Strobe this bit to read data from the flash address identified in
          FLASH_ADDR_REG.
          <li>Prior to strobing this bit verify no read, write, or erase
          operations are in progress, no error bits are asserted, and
          write protection is enabled by reading FLASH_STATUS_REG.</li>
          <li>Attempts to read data while other operations are in progress
          or while write protection is disabled will be ignored.</li>
          <li>After strobing this bit poll the FLASH_READ_IDLE and
          FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when
          the read operation is complete and if it was successful.</li>
          <li>Upon successful completion the data read from flash will be
          available in FLASH_READ_DATA_REG.</li></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">1w</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_DISABLE_WP_STB"></a>FLASH_DISABLE_WP_STB</span><span class="attr"> &nbsp;&nbsp;(Strobe)</span></p>
                <p>Strobe this bit to disable write protection to the section of the
          Max 10 on-chip flash storing the primary configuration image
          (CFM0).
          <li>Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
          determine the current state of write protection.</li>
          <li>Prior to strobing this bit verify no read operations are in
          progress and no error bits are asserted by reading
          FLASH_STATUS_REG.</li>
          <li>Attempts to disable write protection while a read is in
          progress will be ignored.</li>
          <li>Attempts to disable write protection will be ignored if
          this bit is strobed simultaneously with either FLASH_READ_STB
          or FLASH_ENABLE_WP_STB.</li>
          <li>Write protection must be disabled prior to performing erase or
          write operations.</li>
          <li>Upon completion of erase/write operations write protection
          will remain disabled. When not actively erasing or writing a new
          image write protection should be enabled to avoid data
          corruption.</li></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">0w</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ENABLE_WP_STB"></a>FLASH_ENABLE_WP_STB</span><span class="attr"> &nbsp;&nbsp;(Strobe)</span></p>
                <p>Strobe this bit to enable write protection to the section of the
          Max 10 on-chip flash storing the primary configuration image
          (CFM0).
          <li>Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
          determine the current state of write protection.</li>
          <li>Prior to strobing this bit verify no write or erase operations
          are in progress and no error bits are asserted by reading
          FLASH_STATUS_REG.</li>
          <li>Attempts to enable write protection while erase or write
          operations are in progress will be ignored.</li>
          <li>Write protection must be enabled prior to performing
          read operations.</li>
          <li>Write protection should be enabled after completing
          write or erase operations to prevent data corruption.</li></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="RECONFIG_REGMAP|FLASH_ADDR_REG"></a>
            
<h3 class="register">Offset 0x0008: FLASH_ADDR_REG Register (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_ADDR_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_ADDR_REG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_ADDR_REG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|RECONFIG">SPI_REGMAP|RECONFIG</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000020</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">FLASH_ADDR_REG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0008</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000028

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>

</div>

<div class="info">



</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..17</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">16..0</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_ADDR_REG|FLASH_ADDR"></a>FLASH_ADDR</span><span class="attr"> </span></p>
                <p>This field holds the target address for the next read or
          write operation. Set this field prior to strobing the
          FLASH_WRITE_STB and FLASH_READ_STB bits of
          FLASH_CONTROL_REG. Valid addresses are defined by the
          FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration.</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="RECONFIG_REGMAP|FLASH_WRITE_DATA_REG"></a>
            
<h3 class="register">Offset 0x000C: FLASH_WRITE_DATA_REG Register (W)</h3>

                 <a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_WRITE_DATA_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_WRITE_DATA_REG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_WRITE_DATA_REG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|RECONFIG">SPI_REGMAP|RECONFIG</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000020</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">FLASH_WRITE_DATA_REG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x000C</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00002C

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>

</div>

<div class="info">



</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..0w</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_WRITE_DATA_REG|FLASH_WRITE_DATA"></a>FLASH_WRITE_DATA</span><span class="attr"> </span></p>
                <p>Data in this register will be written to the flash at the address
          identified in FLASH_ADDR_REG when a successful write operation
          is executed.</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="RECONFIG_REGMAP|FLASH_READ_DATA_REG"></a>
            
<h3 class="register">Offset 0x0010: FLASH_READ_DATA_REG Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_READ_DATA_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_READ_DATA_REG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_READ_DATA_REG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|RECONFIG">SPI_REGMAP|RECONFIG</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000020</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">FLASH_READ_DATA_REG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0010</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000030

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>

</div>

<div class="info">



</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..0</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_READ_DATA_REG|FLASH_READ_DATA"></a>FLASH_READ_DATA</span><span class="attr"> </span></p>
                <p>This register contains data read from the flash address identified
          in FLASH_ADDR_REG after a successful read operation is executed.</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG"></a>
            
<h3 class="register">Offset 0x0014: FLASH_CFM0_START_ADDR_REG Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|RECONFIG">SPI_REGMAP|RECONFIG</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000020</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">FLASH_CFM0_START_ADDR_REG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0014</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000034

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>

</div>

<div class="info">



</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..0</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG|FLASH_CFM0_START_ADDR"></a>FLASH_CFM0_START_ADDR</span><span class="attr"> </span></p>
                <p>Start address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).</p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG"></a>
            
<h3 class="register">Offset 0x0018: FLASH_CFM0_END_ADDR_REG Register (R)</h3>

                 <a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|RECONFIG">SPI_REGMAP|RECONFIG</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000020</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">FLASH_CFM0_END_ADDR_REG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0018</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000038

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">Initial Value not specified
</p>

<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>

</div>

<div class="info">



</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..0</td>
              <td>
                <p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG|FLASH_CFM0_END_ADDR"></a>FLASH_CFM0_END_ADDR</span><span class="attr"> </span></p>
                <p>Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).</p>
            
              </td>
            </tr>
            
</table>

</div>

</div>

</div>

            <div class="regmap">
              <a name="SPI_REGMAP"></a>
              <h1 class="regmap">SPI_REGMAP</h1>
            
            <div class="group"><a name="SPI_REGMAP|SPI_REGMAP_WINDOWS"></a><h2 class="group">SPI_REGMAP_WINDOWS</h2>
            
            <div class="register">
              <a name="SPI_REGMAP|BASE_WINDOW_SPI"></a>
            
<h3 class="register">Offset 0x0000: BASE_WINDOW_SPI Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#BASIC_REGS_REGMAP">BASIC_REGS_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('SPI_REGMAP|BASE_WINDOW_SPI_in')">(<span id="show_SPI_REGMAP|BASE_WINDOW_SPI_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_SPI_REGMAP|BASE_WINDOW_SPI_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">BASE_WINDOW_SPI</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x20 (32 bytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000000

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">



</div>

</div>

            <div class="register">
              <a name="SPI_REGMAP|RECONFIG"></a>
            
<h3 class="register">Offset 0x0020: RECONFIG Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#RECONFIG_REGMAP">RECONFIG_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('SPI_REGMAP|RECONFIG_in')">(<span id="show_SPI_REGMAP|RECONFIG_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_SPI_REGMAP|RECONFIG_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RECONFIG</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0020</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x20 (32 bytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000020

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">



</div>

</div>

            <div class="register">
              <a name="SPI_REGMAP|POWER_REGS"></a>
            
<h3 class="register">Offset 0x0040: POWER_REGS Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#POWER_REGS_REGMAP">POWER_REGS_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('SPI_REGMAP|POWER_REGS_in')">(<span id="show_SPI_REGMAP|POWER_REGS_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_SPI_REGMAP|POWER_REGS_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">POWER_REGS</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0040</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x20 (32 bytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x000040

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">



</div>

</div>

            <div class="register">
              <a name="SPI_REGMAP|DB_CONTROL_WINDOW_SPI"></a>
            
<h3 class="register">Offset 0x1000: DB_CONTROL_WINDOW_SPI Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#DB_CONTROL_REGMAP">DB_CONTROL_REGMAP</a></p>
                 <a class="sh_addrs" href="javascript:sa('SPI_REGMAP|DB_CONTROL_WINDOW_SPI_in')">(<span id="show_SPI_REGMAP|DB_CONTROL_WINDOW_SPI_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_SPI_REGMAP|DB_CONTROL_WINDOW_SPI_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">DB_CONTROL_WINDOW_SPI</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x1000</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x5000 (20 Kbytes)</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x001000

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info">This window is defined in HDL source file zbx_top_cpld.v.</p>

</div>

<div class="info">



</div>

</div>

</div>

</div>

            <div class="regmap">
              <a name="SWITCH_SETUP_REGMAP"></a>
              <h1 class="regmap">SWITCH_SETUP_REGMAP</h1>
            
            <div class="group"><a name="SWITCH_SETUP_REGMAP|SWITCH_SETUP_REGISTERS"></a><h2 class="group">SWITCH_SETUP_REGISTERS</h2>
            The following registers are used to control the path that the RF signal
      takes for both Tx and Rx<BR/><BR/>
            <div class="register">
              <a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL"></a>
            
<h3 class="register">Offset 0x0000: TX0_PATH_CONTROL(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL_in')">(<span id="show_SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|SWITCH_SETUP_REGS">DB_CONTROL_REGMAP|SWITCH_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">TX0_PATH_CONTROL</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x002000 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x002000 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x00000000</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file switch_control.v.<BR/>
It uses RegType <b>TX_PATH_CONTROL</b> which is defined in HDL source file switch_control.v.</p>

</div>

<div class="info">

This Register controls the switches along the Tx path. Note: default
        values refer to the RX0 path. RX1 has the same defaults, but their
        bit values may differ.<BR/>
This Register controls the Tx0 paths.<br>
        This register array can hold settings for all ATR configurations.
        The register index equals the ATR configuration.
        The active configuration can be selected in <a href="#ATR_REGMAP">ATR_REGMAP</a>.
        Independently all configurations can be read/written at any time.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..27</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">26</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_14"></a>TX_SWITCH_14</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Tx Switch 13 LO path.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx external LO path<BR/>
          Write 1 to select Tx internal LO path<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx internal LO path<BR/>
          Write 1 to select Tx external LO path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">25</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">24</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_13"></a>TX_SWITCH_13</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Tx0 Switch 13 LO path.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx0 internal LO path<BR/>
          Write 1 to select Tx0 external LO path<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx0 external LO path<BR/>
          Write 1 to select Tx0 internal LO path<BR/></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..22</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">21..20</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_11"></a>TX_SWITCH_11</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 11.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx Rx path, <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|RX_SWITCH_1">RX_SWITCH_1</a> must also select the correct path<BR/>
          Write 1 to select Tx highband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_10">TX_SWITCH_10</a> must also match this path.<BR/>
          Write 2 to select Tx lowband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_10">TX_SWITCH_10</a> must also match this path.<BR/>
          Write 3 to select Tx amplifier bypass path<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx Rx path, <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|RX_SWITCH_1">RX_SWITCH_1</a> must also select the correct path<BR/>
          Write 1 to select Tx amplifier bypass path<BR/>
          Write 2 to select Tx lowband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_10">TX_SWITCH_10</a> must also match this path.<BR/>
          Write 3 to select Tx highband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_10">TX_SWITCH_10</a> must also match this path.<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">19..18</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_10"></a>TX_SWITCH_10</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 10.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx amplifier bypass path<BR/>
          Write 1 to select Tx calibration loopback path<BR/>
          Write 2 to select Tx lowband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_11">TX_Switch_11</a> must also match this path.<BR/>
          Write 3 to select Tx highband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_11">TX_Switch_11</a> must also match this path.<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx highband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_11">TX_Switch_11</a> must also match this path.<BR/>
          Write 1 to select Tx lowband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_11">TX_Switch_11</a> must also match this path.<BR/>
          Write 2 to select Tx amplifier bypass path<BR/>
          Write 3 to select Tx calibration loopback path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">17..16</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_9"></a>TX_SWITCH_9</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 9.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx RF3 path, 2.3  GHz to 3.1  GHz<BR/>
          Write 1 to select Tx RF1 path, 1.0  MHz to 1.95 GHz<BR/>
          Write 2 to select Tx RF2 path, 1.95 GHz to 2.3  GHz<BR/>
          Write 3 to select Tx RF4 path, 3.1  GHz to 8.0  GHz<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx RF4 path, 3.1  GHz to 8.0  GHz<BR/>
          Write 1 to select Tx RF2 path, 1.95 GHz to 2.3  GHz<BR/>
          Write 2 to select Tx RF1 path, 1.0  MHz to 1.95 GHz<BR/>
          Write 3 to select Tx RF3 path, 2.3  GHz to 3.1  GHz<BR/></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">14..12</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_8"></a>TX_SWITCH_8</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Tx Switch 8, note this is one hot encoding and not binary.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 1 to select Tx RF3 path, 2.3  GHz to 3.1 GHz<BR/>
          Write 2 to select Tx RF1 path, 1.0  MHz to 1.95 GHz<BR/>
          Write 4 to select Tx RF2 path, 1.95 GHz to 2.3 GHz<BR/>
          <b>FOR TX1:</b><BR/>
          Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz<BR/>
          Write 2 to select Tx RF1 path, 1.0  MHz to 1.95 GHz<BR/>
          Write 4 to select Tx RF3 path, 2.3  GHz to 3.1 GHz<BR/>
          <i>*All other values are invalid</i><BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">11..10</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_7"></a>TX_SWITCH_7</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 7.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select 50 ohm termination<BR/>
          Write 1 to select no connect<BR/>
          Write 2 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz<BR/>
          Write 3 to select Tx lowbands RF1, RF2, RF3 path. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_8">TX_SWITCH_8</a> for those controls<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx lowbands RF1, RF2, RF3 path. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_8">TX_SWITCH_8</a> for those controls<BR/>
          Write 1 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz<BR/>
          Write 2 to select no connect<BR/>
          Write 3 to select 50 ohm termination<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">9..8</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_6"></a>TX_SWITCH_6</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 6.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz<BR/>
          Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz<BR/>
          Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz<BR/>
          Write 3 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_5">TX_SWITCH_5</a> for those controls</font><BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_5">TX_SWITCH_5</a> for those controls</font><BR/>
          Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz<BR/>
          Write 2 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz<BR/>
          Write 3 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz<BR/></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..6</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_5"></a>TX_SWITCH_5</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 5. This switch path is only taken if <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_6">TX_SWITCH_6</a> is set to 0.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz<BR/>
          Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz<BR/>
          Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz<BR/>
          Write 3 to select Tx If1 Filter 50 ohm termination<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx If1 Filter 50 ohm termination<BR/>
          Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz<BR/>
          Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz<BR/>
          Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">5..4</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_4"></a>TX_SWITCH_4</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 4. This switch path is only taken if <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_4">TX_SWITCH_4</a> is set to 0.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select 50 ohm termination<BR/>
          Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz<BR/>
          Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz<BR/>
          Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz<BR/>
          Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz<BR/>
          Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz<BR/>
          Write 3 to select 50 ohm termination<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3..2</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_3"></a>TX_SWITCH_3</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 3. The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_4">TX_SWITCH_4</a> for those controls<BR/>
          Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz<BR/>
          Write 2 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz<BR/>
          Write 3 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz<BR/>
          Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz<BR/>
          Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz<BR/>
          Write 3 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_4">TX_SWITCH_4</a> for those controls<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">1</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">0</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_1_2"></a>TX_SWITCH_1_2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Write 0 to select Tx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz<BR/>
          Write 1 to select Tx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz<BR/></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL"></a>
            
<h3 class="register">Offset 0x0400: TX1_PATH_CONTROL(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL_in')">(<span id="show_SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|SWITCH_SETUP_REGS">DB_CONTROL_REGMAP|SWITCH_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">TX1_PATH_CONTROL</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0400 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x002400 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x002400 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x00000000</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file switch_control.v.<BR/>
It uses RegType <b>TX_PATH_CONTROL</b> which is defined in HDL source file switch_control.v.</p>

</div>

<div class="info">

This Register controls the switches along the Tx path. Note: default
        values refer to the RX0 path. RX1 has the same defaults, but their
        bit values may differ.<BR/>
This Register controls the Tx1 paths.<br>
        This register array can hold settings for all ATR configurations.
        The register index equals the ATR configuration.
        The active configuration can be selected in <a href="#ATR_REGMAP">ATR_REGMAP</a>.
        Independently all configurations can be read/written at any time.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..27</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">26</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_14"></a>TX_SWITCH_14</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Tx Switch 13 LO path.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx external LO path<BR/>
          Write 1 to select Tx internal LO path<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx internal LO path<BR/>
          Write 1 to select Tx external LO path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">25</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">24</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_13"></a>TX_SWITCH_13</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Tx0 Switch 13 LO path.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx0 internal LO path<BR/>
          Write 1 to select Tx0 external LO path<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx0 external LO path<BR/>
          Write 1 to select Tx0 internal LO path<BR/></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23..22</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">21..20</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_11"></a>TX_SWITCH_11</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 11.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx Rx path, <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|RX_SWITCH_1">RX_SWITCH_1</a> must also select the correct path<BR/>
          Write 1 to select Tx highband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_10">TX_SWITCH_10</a> must also match this path.<BR/>
          Write 2 to select Tx lowband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_10">TX_SWITCH_10</a> must also match this path.<BR/>
          Write 3 to select Tx amplifier bypass path<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx Rx path, <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|RX_SWITCH_1">RX_SWITCH_1</a> must also select the correct path<BR/>
          Write 1 to select Tx amplifier bypass path<BR/>
          Write 2 to select Tx lowband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_10">TX_SWITCH_10</a> must also match this path.<BR/>
          Write 3 to select Tx highband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_10">TX_SWITCH_10</a> must also match this path.<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">19..18</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_10"></a>TX_SWITCH_10</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 10.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx amplifier bypass path<BR/>
          Write 1 to select Tx calibration loopback path<BR/>
          Write 2 to select Tx lowband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_11">TX_Switch_11</a> must also match this path.<BR/>
          Write 3 to select Tx highband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_11">TX_Switch_11</a> must also match this path.<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx highband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_11">TX_Switch_11</a> must also match this path.<BR/>
          Write 1 to select Tx lowband amp path. <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_11">TX_Switch_11</a> must also match this path.<BR/>
          Write 2 to select Tx amplifier bypass path<BR/>
          Write 3 to select Tx calibration loopback path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">17..16</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_9"></a>TX_SWITCH_9</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 9.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx RF3 path, 2.3  GHz to 3.1  GHz<BR/>
          Write 1 to select Tx RF1 path, 1.0  MHz to 1.95 GHz<BR/>
          Write 2 to select Tx RF2 path, 1.95 GHz to 2.3  GHz<BR/>
          Write 3 to select Tx RF4 path, 3.1  GHz to 8.0  GHz<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx RF4 path, 3.1  GHz to 8.0  GHz<BR/>
          Write 1 to select Tx RF2 path, 1.95 GHz to 2.3  GHz<BR/>
          Write 2 to select Tx RF1 path, 1.0  MHz to 1.95 GHz<BR/>
          Write 3 to select Tx RF3 path, 2.3  GHz to 3.1  GHz<BR/></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">14..12</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_8"></a>TX_SWITCH_8</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Tx Switch 8, note this is one hot encoding and not binary.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 1 to select Tx RF3 path, 2.3  GHz to 3.1 GHz<BR/>
          Write 2 to select Tx RF1 path, 1.0  MHz to 1.95 GHz<BR/>
          Write 4 to select Tx RF2 path, 1.95 GHz to 2.3 GHz<BR/>
          <b>FOR TX1:</b><BR/>
          Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz<BR/>
          Write 2 to select Tx RF1 path, 1.0  MHz to 1.95 GHz<BR/>
          Write 4 to select Tx RF3 path, 2.3  GHz to 3.1 GHz<BR/>
          <i>*All other values are invalid</i><BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">11..10</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_7"></a>TX_SWITCH_7</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 7.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select 50 ohm termination<BR/>
          Write 1 to select no connect<BR/>
          Write 2 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz<BR/>
          Write 3 to select Tx lowbands RF1, RF2, RF3 path. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_8">TX_SWITCH_8</a> for those controls<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx lowbands RF1, RF2, RF3 path. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_8">TX_SWITCH_8</a> for those controls<BR/>
          Write 1 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz<BR/>
          Write 2 to select no connect<BR/>
          Write 3 to select 50 ohm termination<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">9..8</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_6"></a>TX_SWITCH_6</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 6.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz<BR/>
          Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz<BR/>
          Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz<BR/>
          Write 3 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_5">TX_SWITCH_5</a> for those controls</font><BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_5">TX_SWITCH_5</a> for those controls</font><BR/>
          Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz<BR/>
          Write 2 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz<BR/>
          Write 3 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz<BR/></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7..6</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_5"></a>TX_SWITCH_5</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 5. This switch path is only taken if <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_6">TX_SWITCH_6</a> is set to 0.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz<BR/>
          Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz<BR/>
          Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz<BR/>
          Write 3 to select Tx If1 Filter 50 ohm termination<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx If1 Filter 50 ohm termination<BR/>
          Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz<BR/>
          Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz<BR/>
          Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">5..4</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_4"></a>TX_SWITCH_4</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 4. This switch path is only taken if <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_4">TX_SWITCH_4</a> is set to 0.
          The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select 50 ohm termination<BR/>
          Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz<BR/>
          Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz<BR/>
          Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz<BR/>
          Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz<BR/>
          Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz<BR/>
          Write 3 to select 50 ohm termination<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3..2</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_3"></a>TX_SWITCH_3</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Tx Switch 3. The configuration of this switch changes between TX paths.<BR/>
          <b>FOR TX0:</b><BR/>
          Write 0 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_4">TX_SWITCH_4</a> for those controls<BR/>
          Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz<BR/>
          Write 2 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz<BR/>
          Write 3 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz<BR/>
          <b>FOR TX1:</b><BR/>
          Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz<BR/>
          Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz<BR/>
          Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz<BR/>
          Write 3 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See <a href="#SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL|TX_SWITCH_4">TX_SWITCH_4</a> for those controls<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">1</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">0</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL|TX_SWITCH_1_2"></a>TX_SWITCH_1_2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Write 0 to select Tx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz<BR/>
          Write 1 to select Tx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz<BR/></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL"></a>
            
<h3 class="register">Offset 0x0800: RX0_PATH_CONTROL(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL_in')">(<span id="show_SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|SWITCH_SETUP_REGS">DB_CONTROL_REGMAP|SWITCH_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RX0_PATH_CONTROL</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0800 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x002800 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x002800 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x00000000</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file switch_control.v.<BR/>
It uses RegType <b>RX_PATH_CONTROL</b> which is defined in HDL source file switch_control.v.</p>

</div>

<div class="info">

This Register controls switches along Rx paths. Note: default
        values refer to the RX0 path. RX1 has the same defaults, but their
        bit values may differ.<BR/>
This Register controls the Rx0 paths.<br>
        This register array can hold settings for all ATR configurations.
        The register index equals the ATR configuration.
        The active configuration can be selected in <a href="#ATR_REGMAP">ATR_REGMAP</a>.
        Independently all configurations can be read/written at any time.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">22..20</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_11"></a>RX_SWITCH_11</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Rx Switch 11, note to digital designer: Control V2 is pulled to ground.<BR/><BR/>
          The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 1 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz<BR/>
          Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz<BR/>
          Write 4 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz<BR/>
          <b>FOR RX1:</b><BR/>
          Write 1 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz<BR/>
          Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz<BR/>
          Write 4 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">19</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">18</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_10"></a>RX_SWITCH_10</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Rx Switch 10 LO path. The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx internal LO path<BR/>
          Write 1 to select Rx external LO path<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx external LO path<BR/>
          Write 1 to select Rx internal LO path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">17</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">16</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_9"></a>RX_SWITCH_9</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Rx Switch 9 LO path. The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx internal LO path<BR/>
          Write 1 to select Rx external LO path<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx external LO path<BR/>
          Write 1 to select Rx internal LO path<BR/></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">14</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_7_8"></a>RX_SWITCH_7_8</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Shared control for Rx switch 7 and switch 8.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz<BR/>
          Write 1 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz<BR/>
          Write 1 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">13..12</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6"></a>RX_SWITCH_6</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/><BR/>

          Control for Rx Switch 6. The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">11..10</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_5"></a>RX_SWITCH_5</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/><BR/>

          Control for Rx Switch 5. The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">9</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">8</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_4"></a>RX_SWITCH_4</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is the only control, and control B is tied to ground</font><BR/>
          Control for Rx Switch 4.<BR/>
          Write 0 to select Rx RF1/2 lowband path<BR/>
          Write 1 to select Rx RF3 highband path<BR/></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">6..4</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_3"></a>RX_SWITCH_3</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Rx Switch 3, note this is one hot encoding and not binary.
          The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 1 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz<BR/>
          Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz<BR/>
          Write 4 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz<BR/>
          <b>FOR RX1:</b><BR/>
          Write 1 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz<BR/>
          Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz<BR/>
          Write 4 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz<BR/>
          <i>*All other values are invalid</i><BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">2</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_2"></a>RX_SWITCH_2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is the only control, and control B is pulled high</font><BR/>
          Control for Rx Switch 2. The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx RF3 highband path<BR/>
          Write 1 to select Rx RF1/2 lowband path<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx RF1/2 lowband path<BR/>
          Write 1 to select Rx RF3 highband path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">1..0</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_1"></a>RX_SWITCH_1</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Rx Switch 1.
          The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx calibration loopback<BR/>
          Write 1 to select Rx 50 ohm termination path<BR/>
          Write 2 to select Tx Rx path, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|TX_SWITCH_11">TX_SWITCH_11</a> must also select the correct path<BR/>
          Write 3 to select Rx input port<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx calibration loopback<BR/>
          Write 1 to select Tx Rx path, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|TX_SWITCH_11">TX_SWITCH_11</a> must also select the correct path<BR/>
          Write 2 to select Rx input port<BR/>
          Write 3 to select Rx 50 ohm termination path<BR/></p>
            
              </td>
            </tr>
            
</table>

</div>

            <div class="register">
              <a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL"></a>
            
<h3 class="register">Offset 0x0C00: RX1_PATH_CONTROL(255:0) Register Array (R|W)</h3>

                 <a class="sh_addrs" href="javascript:sa('SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL_in')">(<span id="show_SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL_in">show</span> extended info)</a>
                 <div class="sh_addrs" id="div_SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL_in">
                 
                <table class="extended_info">
                
<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|GPIO">GPIO</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO">GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#DB_CONTROL_REGMAP|SWITCH_SETUP_REGS">DB_CONTROL_REGMAP|SWITCH_SETUP_REGS</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="2">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right">RX1_PATH_CONTROL</td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0C00 + i*4</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x002C00 + i*4

</td></tr>
</table>

</td>

</tr>

<tr>

<td class="outercell" rowspan="1">

                  <table border="0" cellspacing="0" cellpadding="0">
                    <tr><td class="offset_info" align="right">Port <a href="#ZBX_CPLD|SPI">SPI</a></td></tr>
                  </table>
               
</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">
  <tr><td class="offset_info" align="right"><a href="#SPI_REGMAP|DB_CONTROL_WINDOW_SPI">SPI_REGMAP|DB_CONTROL_WINDOW_SPI</a></td></tr>
  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x001000</td></tr>
</table>

</td>

<td class="outercell" rowspan="1">

<table border="0" cellspacing="0" cellpadding="0">

<tr><td class="offset_info">


Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x002C00 + i*4

</td></tr>
</table>

</td>

</tr>

</table><p/>

<p class="reg_info"><B>Initial Values</B><BR/>
<table>
  <tr><td>default</td><td>=&gt;</td><td>0x00000000</td></tr>
</table>
</p>

<p class="reg_info">This register is defined in HDL source file switch_control.v.<BR/>
It uses RegType <b>RX_PATH_CONTROL</b> which is defined in HDL source file switch_control.v.</p>

</div>

<div class="info">

This Register controls switches along Rx paths. Note: default
        values refer to the RX0 path. RX1 has the same defaults, but their
        bit values may differ.<BR/>
This Register controls the Rx1 paths.<br>
        This register array can hold settings for all ATR configurations.
        The register index equals the ATR configuration.
        The active configuration can be selected in <a href="#ATR_REGMAP">ATR_REGMAP</a>.
        Independently all configurations can be read/written at any time.

</div>

                <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
                  <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
                
            <tr  valign="top">
              <td class="bits">31..24</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">23</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">22..20</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL|RX_SWITCH_11"></a>RX_SWITCH_11</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Rx Switch 11, note to digital designer: Control V2 is pulled to ground.<BR/><BR/>
          The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 1 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz<BR/>
          Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz<BR/>
          Write 4 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz<BR/>
          <b>FOR RX1:</b><BR/>
          Write 1 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz<BR/>
          Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz<BR/>
          Write 4 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">19</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">18</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL|RX_SWITCH_10"></a>RX_SWITCH_10</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Rx Switch 10 LO path. The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx internal LO path<BR/>
          Write 1 to select Rx external LO path<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx external LO path<BR/>
          Write 1 to select Rx internal LO path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">17</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">16</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL|RX_SWITCH_9"></a>RX_SWITCH_9</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Rx Switch 9 LO path. The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx internal LO path<BR/>
          Write 1 to select Rx external LO path<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx external LO path<BR/>
          Write 1 to select Rx internal LO path<BR/></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">15</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">14</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL|RX_SWITCH_7_8"></a>RX_SWITCH_7_8</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Shared control for Rx switch 7 and switch 8.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz<BR/>
          Write 1 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz<BR/>
          Write 1 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">13..12</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL|RX_SWITCH_6"></a>RX_SWITCH_6</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/><BR/>

          Control for Rx Switch 6. The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">11..10</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL|RX_SWITCH_5"></a>RX_SWITCH_5</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/><BR/>

          Control for Rx Switch 5. The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/>
          Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|RX_SWITCH_6">RX_SWITCH_6</a> must also select this path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">9</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">8</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL|RX_SWITCH_4"></a>RX_SWITCH_4</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is the only control, and control B is tied to ground</font><BR/>
          Control for Rx Switch 4.<BR/>
          Write 0 to select Rx RF1/2 lowband path<BR/>
          Write 1 to select Rx RF3 highband path<BR/></p>
            
              </td>
            </tr>
            
            <tr class='byte' valign="top">
              <td class="bits">7</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">6..4</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL|RX_SWITCH_3"></a>RX_SWITCH_3</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p>Control for Rx Switch 3, note this is one hot encoding and not binary.
          The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 1 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz<BR/>
          Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz<BR/>
          Write 4 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz<BR/>
          <b>FOR RX1:</b><BR/>
          Write 1 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz<BR/>
          Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz<BR/>
          Write 4 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz<BR/>
          <i>*All other values are invalid</i><BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">3</td>
              <td>
                <p><span class="name">Reserved</span><span class="attr"> </span></p>
                <p></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">2</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL|RX_SWITCH_2"></a>RX_SWITCH_2</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is the only control, and control B is pulled high</font><BR/>
          Control for Rx Switch 2. The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx RF3 highband path<BR/>
          Write 1 to select Rx RF1/2 lowband path<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx RF1/2 lowband path<BR/>
          Write 1 to select Rx RF3 highband path<BR/></p>
            
              </td>
            </tr>
            
            <tr  valign="top">
              <td class="bits">1..0</td>
              <td>
                <p><span class="name"><a name="SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL|RX_SWITCH_1"></a>RX_SWITCH_1</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
                <p><font color="red">note to digital designer: control A is LSB, and control B is MSB</font><BR/>
          Control for Rx Switch 1.
          The configuration of this switch changes between RX paths.<BR/>
          <b>FOR RX0:</b><BR/>
          Write 0 to select Rx calibration loopback<BR/>
          Write 1 to select Rx 50 ohm termination path<BR/>
          Write 2 to select Tx Rx path, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|TX_SWITCH_11">TX_SWITCH_11</a> must also select the correct path<BR/>
          Write 3 to select Rx input port<BR/>
          <b>FOR RX1:</b><BR/>
          Write 0 to select Rx calibration loopback<BR/>
          Write 1 to select Tx Rx path, <a href="#SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL|TX_SWITCH_11">TX_SWITCH_11</a> must also select the correct path<BR/>
          Write 2 to select Rx input port<BR/>
          Write 3 to select Rx 50 ohm termination path<BR/></p>
            
              </td>
            </tr>
            
</table>

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